parisc: lba: Convert LBA PCI bus driver to use arch_initcall()

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: Avoid ioremap() for same addresss in iosapic_register()

The LBA has already called ioremap() to get it's virtual address,
which can be used for the IOSAPIC as well.
Avoid calling ioremap() a

parisc: Avoid ioremap() for same addresss in iosapic_register()

The LBA has already called ioremap() to get it's virtual address,
which can be used for the IOSAPIC as well.
Avoid calling ioremap() again and just reuse the correct
iomem address for the IOSAPIC.

Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: Move init function declarations into header file

Clean up the code to not have external function declarations
inside the C source files. Reduces warnings when compiled with W=1.

Signed-off-

parisc: Move init function declarations into header file

Clean up the code to not have external function declarations
inside the C source files. Reduces warnings when compiled with W=1.

Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: lba_pci: Mark two variables __maybe_unused

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: Check the return value of ioremap() in lba_driver_probe()

The function ioremap() in lba_driver_probe() can fail, so
its return value should be checked.

Fixes: 4bdc0d676a643 ("remove ioremap

parisc: Check the return value of ioremap() in lba_driver_probe()

The function ioremap() in lba_driver_probe() can fail, so
its return value should be checked.

Fixes: 4bdc0d676a643 ("remove ioremap_nocache and devm_ioremap_nocache")
Reported-by: Hacash Robot <hacashRobot@santino.com>
Signed-off-by: William Dean <williamsukatube@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v5.6+

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remove ioremap_nocache and devm_ioremap_nocache

ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

Signed-off-by: Chr

remove ioremap_nocache and devm_ioremap_nocache

ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

Based on 1 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license as published by
the free software foundation either version 2 of the license or at
your option any later version

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 3029 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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parisc: remove the HBA_DATA macro

No need to hide a cast in a macro, especially as all users have
cleaner ways to archive the result than blind casting.

Signed-off-by: Christoph Hellwig <hch@lst.de

parisc: remove the HBA_DATA macro

No need to hide a cast in a macro, especially as all users have
cleaner ways to archive the result than blind casting.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Helge Deller <deller@gmx.de>

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parisc/lba_pci: use container_of in LBA_DEV

Use the type safe container_of macros instead of a blind cast in
LBA_DEV, and turn the macro into an inline function.

Signed-off-by: Christoph Hellwig <h

parisc/lba_pci: use container_of in LBA_DEV

Use the type safe container_of macros instead of a blind cast in
LBA_DEV, and turn the macro into an inline function.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: move internal implementation details out of <asm/dma-mapping.h>

Move everything that is not required for the public facing DMA API out
of <asm/dma-mapping.h> and into a new drivers/parisc/io

parisc: move internal implementation details out of <asm/dma-mapping.h>

Move everything that is not required for the public facing DMA API out
of <asm/dma-mapping.h> and into a new drivers/parisc/iommu.h header.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: Hide built-in serial aux port of Tosca GSP card

Similar to commit bcf3f1752a62 ("parisc: Hide Diva-built-in serial aux and
graphics card") it's better to hide the built-in serial AUX port at

parisc: Hide built-in serial aux port of Tosca GSP card

Similar to commit bcf3f1752a62 ("parisc: Hide Diva-built-in serial aux and
graphics card") it's better to hide the built-in serial AUX port at bootup.
When not hiding the port, the Linux serial driver will try to manage this port
and fails on a A500 server like this:

serial 0000:00:05.0: enabling device (0000 -> 0003)
serial 0000:00:05.0: enabling SERR and PARITY (0003 -> 0143)
0000:00:05.0: ttyS3 at MMIO 0xfffffffff8005000 (irq = 71, base_baud = 115200) is a 16550A
serial 0000:00:05.0: Couldn't register serial port 0, irq 71, type 2, error -28

Signed-off-by: Helge Deller <deller@gmx.de>

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parisc/pci: Switch LBA PCI bus from Hard Fail to Soft Fail mode

Carlo Pisani noticed that his C3600 workstation behaved unstable during heavy
I/O on the PCI bus with a VIA VT6421 IDE/SATA PCI card.

parisc/pci: Switch LBA PCI bus from Hard Fail to Soft Fail mode

Carlo Pisani noticed that his C3600 workstation behaved unstable during heavy
I/O on the PCI bus with a VIA VT6421 IDE/SATA PCI card.

To avoid such instability, this patch switches the LBA PCI bus from Hard Fail
mode into Soft Fail mode. In this mode the bus will return -1UL for timed out
MMIO transactions, which is exactly how the x86 (and most other architectures)
PCI busses behave.

This patch is based on a proposal by Grant Grundler and Kyle McMartin 10
years ago:
https://www.spinics.net/lists/linux-parisc/msg01027.html

Cc: Carlo Pisani <carlojpisani@gmail.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Reviewed-by: Grant Grundler <grantgrundler@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: Hide Diva-built-in serial aux and graphics card

Diva GSP card has built-in serial AUX port and ATI graphic card which simply
don't work and which both don't have external connectors. User G

parisc: Hide Diva-built-in serial aux and graphics card

Diva GSP card has built-in serial AUX port and ATI graphic card which simply
don't work and which both don't have external connectors. User Guides even
mention that those devices shouldn't be used.
So, prevent that Linux drivers try to enable those devices.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # v3.0+

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parisc: Fix up devices below a PCI-PCI MegaRAID controller bridge

A MegaRAID PCI card in my rp5470 acts as PCI-PCI bridge.
Resource allocation for PCI devices behind such a bridge is quite incomplet

parisc: Fix up devices below a PCI-PCI MegaRAID controller bridge

A MegaRAID PCI card in my rp5470 acts as PCI-PCI bridge.
Resource allocation for PCI devices behind such a bridge is quite incomplete,
so that syslog reports those warnings:

LBA 0:10: PCI host bridge to bus 0000:50
pci_bus 0000:50: root bus resource [io 0x80000-0x8ffff] (bus address [0x0000-0xffff])
pci_bus 0000:50: root bus resource [mem 0xffffffff94000000-0xffffffff95ffffff] (bus address [0x94000000-0x95ffffff])
pci_bus 0000:50: root bus resource [bus 50-57]
pci 0000:50:00.0: [8086:0964] type 01 class 0x060400
pci 0000:50:00.1: [8086:1960] type 00 class 0x0e0001
pci 0000:50:00.1: reg 0x10: [mem 0x00000000-0x003fffff pref]
pci 0000:50:00.1: reg 0x30: [mem 0x00000000-0x00007fff pref]
pci 0000:50:00.0: Changing bridge control from 0x00000000 to 0x00000023
pci_bus 0000:51: busn_res: can not insert [bus 51-ff] under [bus 50-57] (conflicts with (null) [bus 50-57])
pci 0000:50:00.0: PCI bridge to [bus 51-ff]
pci 0000:50:00.0: bridge window [io 0x80000-0x80fff]
pci 0000:50:00.0: bridge window [mem 0x00000000-0x000fffff]
pci 0000:50:00.0: bridge window [mem 0x00000000-0x000fffff pref]
pci 0000:50:00.0: can't claim BAR 14 [mem 0x00000000-0x000fffff]: no compatible bridge window
pci 0000:50:00.0: can't claim BAR 15 [mem 0x00000000-0x000fffff pref]: no compatible bridge window
pci 0000:50:00.0: can't claim BAR 16 [??? 0x00000000 flags 0x0]: no compatible bridge window
pci_bus 0000:51: busn_res: [bus 51-ff] end is updated to 51
pci 0000:50:00.0: BAR 16: [??? 0x00000000 flags 0x20000000] has bogus alignment
pci 0000:50:00.1: BAR 0: assigned [mem 0xffffffff94000000-0xffffffff943fffff pref]
pci 0000:50:00.0: BAR 14: assigned [mem 0xffffffff94400000-0xffffffff944fffff]
pci 0000:50:00.0: BAR 15: assigned [mem 0xffffffff94500000-0xffffffff945fffff pref]
pci 0000:50:00.1: BAR 6: assigned [mem 0xffffffff94600000-0xffffffff94607fff pref]
pci 0000:50:00.0: PCI bridge to [bus 51]
pci 0000:50:00.0: bridge window [io 0x80000-0x80fff]
pci 0000:50:00.0: bridge window [mem 0xffffffff94400000-0xffffffff944fffff]
pci 0000:50:00.0: bridge window [mem 0xffffffff94500000-0xffffffff945fffff pref]

The patch below tries to improve the resource allocation.
Output is now:

LBA 0:10: PCI host bridge to bus 0000:50
pci_bus 0000:50: root bus resource [io 0x80000-0x8ffff] (bus address [0x0000-0xffff])
pci_bus 0000:50: root bus resource [mem 0xffffffff94000000-0xffffffff95ffffff] (bus address [0x94000000-0x95ffffff])
pci_bus 0000:50: root bus resource [bus 50-57]
pci 0000:50:00.0: Changing bridge control from 0x00000000 to 0x00000023
pci 0000:50:00.0: PCI bridge to [bus 51-ff]
pci 0000:50:00.1: BAR 0: assigned [mem 0xffffffff94000000-0xffffffff943fffff pref]
pci 0000:50:00.1: BAR 6: assigned [mem 0xffffffff94400000-0xffffffff94407fff pref]
pci 0000:50:00.0: PCI bridge to [bus 51]
pci 0000:50:00.0: bridge window [io 0x80000-0x80fff]

Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: Fix section mismatches in parisc core drivers

Signed-off-by: Helge Deller <deller@gmx.de>

parisc: DMA API: return error instead of BUG_ON for dma ops on non dma devs

Enabling parport pc driver on a B2600 (and probably other 64bit PARISC
systems) produced following BUG:

CPU: 0 PID: 1 Com

parisc: DMA API: return error instead of BUG_ON for dma ops on non dma devs

Enabling parport pc driver on a B2600 (and probably other 64bit PARISC
systems) produced following BUG:

CPU: 0 PID: 1 Comm: swapper Not tainted 4.12.0-rc5-30198-g1132d5e #156
task: 000000009e050000 task.stack: 000000009e04c000

YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00001000000001101111111100001111 Not tainted
r00-03 000000ff0806ff0f 000000009e04c990 0000000040871b78 000000009e04cac0
r04-07 0000000040c14de0 ffffffffffffffff 000000009e07f098 000000009d82d200
r08-11 000000009d82d210 0000000000000378 0000000000000000 0000000040c345e0
r12-15 0000000000000005 0000000040c345e0 0000000000000000 0000000040c9d5e0
r16-19 0000000040c345e0 00000000f00001c4 00000000f00001bc 0000000000000061
r20-23 000000009e04ce28 0000000000000010 0000000000000010 0000000040b89e40
r24-27 0000000000000003 0000000000ffffff 000000009d82d210 0000000040c14de0
r28-31 0000000000000000 000000009e04ca90 000000009e04cb40 0000000000000000
sr00-03 0000000000000000 0000000000000000 0000000000000000 0000000000000000
sr04-07 0000000000000000 0000000000000000 0000000000000000 0000000000000000

IASQ: 0000000000000000 0000000000000000 IAOQ: 00000000404aece0 00000000404aece4
IIR: 03ffe01f ISR: 0000000010340000 IOR: 000001781304cac8
CPU: 0 CR30: 000000009e04c000 CR31: 00000000e2976de2
ORIG_R28: 0000000000000200
IAOQ[0]: sba_dma_supported+0x80/0xd0
IAOQ[1]: sba_dma_supported+0x84/0xd0
RP(r2): parport_pc_probe_port+0x178/0x1200

Cause is a call to dma_coerce_mask_and_coherenet in parport_pc_probe_port,
which PARISC DMA API doesn't handle very nicely. This commit gives back
DMA_ERROR_CODE for DMA API calls, if device isn't capable of DMA
transaction.

Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: Initialize PCI bridge cache line and default latency

PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.

This partly reverts
com

parisc: Initialize PCI bridge cache line and default latency

PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.

This partly reverts
commit 5f0e9b4 ("parisc: Remove unused pcibios_init_bus()")

Signed-off-by: Helge Deller <deller@gmx.de>

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parisc: reduce syslog debug output

Signed-off-by: Helge Deller <deller@gmx.de>

PCI: Revert "PCI: Call pci_read_bridge_bases() from core instead of arch code"

Revert dff22d2054b5 ("PCI: Call pci_read_bridge_bases() from core instead
of arch code").

Reading PCI bridge windows i

PCI: Revert "PCI: Call pci_read_bridge_bases() from core instead of arch code"

Revert dff22d2054b5 ("PCI: Call pci_read_bridge_bases() from core instead
of arch code").

Reading PCI bridge windows is not arch-specific in itself, but there is PCI
core code that doesn't work correctly if we read them too early. For
example, Hannes found this case on an ARM Freescale i.mx6 board:

pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff]
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window)
pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000]
pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000]
pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100]

The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs
0x204100 of space, and mem windows are megabyte-aligned.

Bus sizing can increase a bridge window size, but never *decrease* it (see
d65245c3297a ("PCI: don't shrink bridge resources")). Prior to
dff22d2054b5, ARM didn't read bridge windows at all, so the "original size"
was zero, and we assigned a 3MB window.

After dff22d2054b5, we read the bridge windows before sizing the bus. The
firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since
we never decrease the size, we kept 16MB even though we only needed 3MB.
But 16MB doesn't fit in the host bridge aperture, so we failed to assign
space for the window and the downstream devices.

I think this is a defect in the PCI core: we shouldn't rely on the firmware
to assign sensible windows.

Ray reported a similar problem, also on ARM, with Broadcom iProc.

Issues like this are too hard to fix right now, so revert dff22d2054b5.

Reported-by: Hannes <oe5hpm@gmail.com>
Reported-by: Ray Jui <rjui@broadcom.com>
Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com
Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.com
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

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PCI,parisc: Enable 64-bit bus addresses on PA-RISC

Commit 3a9ad0b ("PCI: Add pci_bus_addr_t") unconditionally introduced usage of
64-bit PCI bus addresses on all 64-bit platforms which broke PA-RISC

PCI,parisc: Enable 64-bit bus addresses on PA-RISC

Commit 3a9ad0b ("PCI: Add pci_bus_addr_t") unconditionally introduced usage of
64-bit PCI bus addresses on all 64-bit platforms which broke PA-RISC.

It turned out that due to enabling the 64-bit addresses, the PCI logic decided
to use the GMMIO instead of the LMMIO region. This commit simply disables
registering the GMMIO and thus we fall back to use the LMMIO region as before.

Reverts commit 45ea2a5fed6dacb9bb0558d8b21eacc1c45d5bb4
("PCI: Don't use 64-bit bus addresses on PA-RISC")

To: linux-parisc@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Meelis Roos <mroos@linux.ee>
Cc: stable@vger.kernel.org # v3.19+
Signed-off-by: Helge Deller <deller@gmx.de>

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PCI: Call pci_read_bridge_bases() from core instead of arch code

When we scan a PCI bus, we read PCI-PCI bridge window registers with
pci_read_bridge_bases() so we can validate the resource hierarch

PCI: Call pci_read_bridge_bases() from core instead of arch code

When we scan a PCI bus, we read PCI-PCI bridge window registers with
pci_read_bridge_bases() so we can validate the resource hierarchy. Most
architectures call pci_read_bridge_bases() from pcibios_fixup_bus(), but
PCI-PCI bridges are not arch-specific, so this doesn't need to be in
arch-specific code.

Call pci_read_bridge_bases() directly from the PCI core instead of from
arch code.

For alpha and mips, we now call pci_read_bridge_bases() always; previously
we only called it if PCI_PROBE_ONLY was set.

[bhelgaas: changelog]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Ralf Baechle <ralf@linux-mips.org>
CC: James E.J. Bottomley <jejb@parisc-linux.org>
CC: Michael Ellerman <mpe@ellerman.id.au>
CC: Bjorn Helgaas <bhelgaas@google.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: David Howells <dhowells@redhat.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Tony Luck <tony.luck@intel.com>
CC: David S. Miller <davem@davemloft.net>
CC: Ingo Molnar <mingo@redhat.com>
CC: Guenter Roeck <linux@roeck-us.net>
CC: Michal Simek <monstr@monstr.eu>
CC: Chris Zankel <chris@zankel.net>

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parisc/PCI: Clip bridge windows to fit in upstream windows

Every PCI-PCI bridge window should fit inside an upstream bridge window
because orphaned address space is unreachable from the primary side

parisc/PCI: Clip bridge windows to fit in upstream windows

Every PCI-PCI bridge window should fit inside an upstream bridge window
because orphaned address space is unreachable from the primary side of the
upstream bridge. If we inherit invalid bridge windows that overlap an
upstream window from firmware, clip them to fit and update the bridge
accordingly.

[bhelgaas: changelog]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik <kordikmarek@gmail.com>
Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: "James E.J. Bottomley" <jejb@parisc-linux.org>
CC: Helge Deller <deller@gmx.de>
CC: linux-parisc@vger.kernel.org

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PCI: Delay enabling bridges until they're needed

We currently enable PCI bridges after scanning a bus and assigning
resources. This is often done in arch code.

This patch changes this so we don't

PCI: Delay enabling bridges until they're needed

We currently enable PCI bridges after scanning a bus and assigning
resources. This is often done in arch code.

This patch changes this so we don't enable a bridge until necessary, i.e.,
until we enable a PCI device behind the bridge. We do this in the generic
pci_enable_device() path, so this also removes the arch-specific code to
enable bridges.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

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parisc: fix LMMIO mismatch between PAT length and MASK register

The LMMIO length reported by PAT and the length given by the LBA MASK
register are not consistent. This leads e.g. to a not-working AT

parisc: fix LMMIO mismatch between PAT length and MASK register

The LMMIO length reported by PAT and the length given by the LBA MASK
register are not consistent. This leads e.g. to a not-working ATI FireGL
card with the radeon DRM driver since the memory can't be mapped.

Fix this by correctly adjusting the resource sizes.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # 3.10

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parisc/PCI: lba: fix: convert to pci_create_root_bus() for correct root bus resources (v2)

commit dc7dce280a
Author: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri Oct 28 16:27:27 2011 -0600
par

parisc/PCI: lba: fix: convert to pci_create_root_bus() for correct root bus resources (v2)

commit dc7dce280a
Author: Bjorn Helgaas <bhelgaas@google.com>
Date: Fri Oct 28 16:27:27 2011 -0600
parisc/PCI: lba: convert to pci_create_root_bus() for correct root bus
resources

Supply root bus resources to pci_create_root_bus() so they're correct
immediately. This fixes the problem of "early" and "header" quirks seeing
incorrect root bus resources.

added tests for elmmio_space.start while it should use
elmmio_space.flags. This for example led to incorrect resource
assignments and a non-working stifb framebuffer on most parisc machines.

LBA 10:1: PCI host bridge to bus 0000:01
pci_bus 0000:01: root bus resource [io 0x12000-0x13fff] (bus address [0x2000-0x3fff])
pci_bus 0000:01: root bus resource [mem 0xfffffffffa000000-0xfffffffffbffffff] (bus address [0xfa000000-0xfbffffff])
pci_bus 0000:01: root bus resource [mem 0xfffffffff4800000-0xfffffffff4ffffff] (bus address [0xf4800000-0xf4ffffff])
pci_bus 0000:01: root bus resource [??? 0x00000001 flags 0x0]

Signed-off-by: Helge Deller <deller@gmx.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>

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