bcm2835_intr.c: fix !MULTIPROCESSOR

Tested on Raspberry PI 3 model A+.

pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
I

pic: Update ci_cpl in pic_set_priority callback.

Not all ICs need interrupts disabled to update the priority. DAIF accesses
are not cheap, so push the update of ci_cpl from pic_set_priority to the
IC's pic_set_priority callback, and let the IC driver determine whether
or not it needs interrupts disabled.

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Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state f

Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.

The AP initialisation code in cpu_init_secondary_processor will read and
initialise the required system registers and state for the BP to attach
and report.

Rework the interrupt handler code for this new sequence. Thankfully,
this removes a bunch of code for bcm2836mp.

The VFP detection handler on <= armv7 relies on the global undefined
handler being in place until the BP attaches vfp. That is, after the
APs have been spun up.

gicv3_its.c has a serialisation issue which is protected against in
the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin
lock. The serialisation issue needs addressing more completely.

Tested on RPI3, Apple M1, QEMU, and lx2k

Fixes PR port-arm/56264:
diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3

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Fix build for uniprocessor.

Install IPI handler with non-NULL context.

A side effect of interrupt handlers with NULL context when using armpic
is that the interrupt handler is only called from interrupt context, not
when lower

Install IPI handler with non-NULL context.

A side effect of interrupt handlers with NULL context when using armpic
is that the interrupt handler is only called from interrupt context, not
when lowering spl!

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PR port-arm/56264

Register all PICs when bcmicu1 is attached, in order to avoid calling
pic_add() from cpu_hatch(), which blocks for aarch64 kernel on RPI3.
This prevented MP kernel to boot due to K

PR port-arm/56264

Register all PICs when bcmicu1 is attached, in order to avoid calling
pic_add() from cpu_hatch(), which blocks for aarch64 kernel on RPI3.
This prevented MP kernel to boot due to KASSERT failure as described
in the PR.

This is a kind of a workaround; the real fix should be to

(a) reorganize cpu_hatch() for aarch64 and arm:
http://mail-index.netbsd.org/port-arm/2021/06/21/msg007320.html

(b) or change MI abstraction of ``MP ready'':
http://mail-index.netbsd.org/port-arm/2021/06/22/msg007327.html

However, still, this fix does not bring about any penalty, and it is
not good to leave RPI3 broken for months...

Tested on RPI3 (aarch64 MP, armv7hf MP) as well as RPI1 (armv6hf UP).

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Move interrupt register definitions to driver.

Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all c

Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.

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Since we're using designated initialisers for compat data, we should
use a completely empty initializer for the sentinel.

Use device_compatible_entry / of_search_compatible() rather than
matching against multiple sets of compatibility strings.

Add 'const char *xname' arg to fdtbus_interrupt_controller_func .establish

interupt -> interrupt

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
dri

Various updates and improvements to cpu start up on arm/aarch64

- start sharing more code around the AP startup messaging.
- call arm_cpu_topology_set early so that ci_core_id is available for
drivers, e.g. bcm2835_intr.c
- both arm and aarch64 now have
- a static cpu_info_store array
- the same arm_cpu_{hatched,mbox}

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use arm_cpu_mpidr() and fix arm64 builds.

ci_core_id isn't setup early enough after recent arm_cpu_topology
changes, so use ci_mpidr as a stop gap fix for cpuid

Use PIC_IRQBASE_ALLOC for all pic_add calls and track/use each cpu irqbase

Use PIC_IRQBASE_ALLOC and allow conditional attachment of interrupt
handlers (for RPI4)

Account for the IRQ offset on the bcm2836.

Jared points out that interrupt_distribute(9) assumes that any interrupt
handle can be used as an input to the MD interrupt_distribute implementation
so we are forced to return the handle we got back

Jared points out that interrupt_distribute(9) assumes that any interrupt
handle can be used as an input to the MD interrupt_distribute implementation
so we are forced to return the handle we got back from intr_establish().
Upshot is that the input to bcm2835_icu_fdt_disestablish() is ambiguous for
shared IRQs, rendering them un-disestablishable.

While here, make sure to actually bump the intr_refcnt, and add an
assertion on the value we get back from bcm2835_icu_fdt_decode_irq().

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There are some devices on the bcm283x that share IRQs (notably, the i2c
controllers), but the generic ARM PIC code doesn't support this. Add a
workaround inspired by the GICv3 driver (thanks Jared f

There are some devices on the bcm283x that share IRQs (notably, the i2c
controllers), but the generic ARM PIC code doesn't support this. Add a
workaround inspired by the GICv3 driver (thanks Jared for pointint it out).

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Sprinkle KASSERTs

Sprinkle static

KNF

Whitespace

Fix to show counters of "bcm2836 pic" by "intrctl list" correctly.