| #
22bcc3fe |
| 10-Aug-2018 |
maxv <maxv@NetBSD.org> |
Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of
acorn26.
ok jmcneill@ skrll@
|
| #
9217c223 |
| 25-Aug-2017 |
christos <christos@NetBSD.org> |
fix the build (rump does not have opt_foo.h)
|
| #
2c34e620 |
| 24-Aug-2017 |
jmcneill <jmcneill@NetBSD.org> |
Do runtime detection of MP extensions to allow using a MULTIPROCESSOR
kernel on CPUs without the MP extensions feature (like Cortex-A8).
|
| #
926fa724 |
| 14-May-2015 |
hsuenaga <hsuenaga@NetBSD.org> |
add synchronization barrier for AURORA_IO_CACHE_COHERENCY.
cleanup MARVELL L2 cache code.
|
| #
d5465e0f |
| 15-Apr-2015 |
hsuenaga <hsuenaga@NetBSD.org> |
clean up cpufuncs of CPU_PJ4B.
PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
- Marvell specific registers
- workaround of errata
- and Marvell spec
clean up cpufuncs of CPU_PJ4B.
PJ4B is a ARMv7 compatible CPU, so most of cpufuncs are just redundant.
we need funcs for:
- Marvell specific registers
- workaround of errata
- and Marvell specific L2 cache maintainance
if I/O coherency fabric is enabled(option AURORA_IO_CACHE_COHERENCY),
probaly we don't need to maintain L2 cache by software.
show more ...
|
| #
42d83c45 |
| 13-Sep-2014 |
matt <matt@NetBSD.org> |
vm_offset_t -> vaddr_t, vm_size_t -> vsize_t
nuke vm_offset_t and vm_size_t
|
| #
0b832a20 |
| 19-Apr-2014 |
matt <matt@NetBSD.org> |
Move xscale cpu_cpwait back from cpufunc_proto.ht to cpufunc.h
|
| #
4f91d8f5 |
| 14-Apr-2014 |
matt <matt@NetBSD.org> |
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
Move prototypes out to <arm/cpufunc.h> to their own file.
Add sdcache routines to cpufunc_asm_sheeva.S
Add code sheeve_setup to init the sdcache and sdcache info.
show more ...
|