- change struct rk_cru_arm and RK_CPU macros to allow mux and div registers to be specified independently.
Allow more div-regs to be specified in the future.
- commonize RK*_PLL() macro.

Make .reg1 and .reg2 of struct rk_cru_cpu_rate into array, and change the type of those to bus_size_t and uint32_t.
Array size may increase in the future.

arm: rockchip: Add support for RK3288 SoC.

The Rockchip RK3288 is a quad core Cortex-A17 SoC.

Fix signed integer overflow found by kUBSan. OK'd by jmcneill.

The output was:
UBSan: Undefined Behavior in ../../../../arch/arm/rockchip/rk3399_cru.c:
284:13, signed integer overflow: 594000

Fix signed integer overflow found by kUBSan. OK'd by jmcneill.

The output was:
UBSan: Undefined Behavior in ../../../../arch/arm/rockchip/rk3399_cru.c:
284:13, signed integer overflow: 594000000 - -2086967296 cannot be
represented in type 'int'

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Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all c

Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.

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Rockchip crypto engine RNG driver.

As found on the rk3288 and rk3399. This driver only supports the
TRNG, not the rest of the crypto engine, although it uses the AES unit
to do a self-test at attac

Rockchip crypto engine RNG driver.

As found on the rk3288 and rk3399. This driver only supports the
TRNG, not the rest of the crypto engine, although it uses the AES unit
to do a self-test at attach time to verify that the engine works.

There seem to be two versions of the Rockchip crypto engine, v1 and
v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll
clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto'
later on.

The crypto binding derived from the Rockchip BSP Linux kernel, in the
location it appears on the rk3399, is in rk3399-crypto.dtsi, since
there doesn't seem to be a better place to put it at the moment among
this twisty maze of inclusions, all different.

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Add 2000 MHz to available armclkb rates

rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac.

The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div.
vpll is apparently used directly as a pixel clock source for the
H

rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac.

The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div.
vpll is apparently used directly as a pixel clock source for the
HDMI PHY, and we don't want the other VOP's dclk changing out from
under it because we can't handle finding a replacement clock source
with the right rate yet.

gpll happens to run at 594MHz, which works well as a basis for pixel
clocks.

Linux suggests that the source clock of the fractional divider needs
to be more than twenty times greater than the resulting clock (or some
intermediate clock?) for output stability. This may not be the case
with 594MHz and the common pixel clocks I see used by displays in my
area of the wild, but it works for now.

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rk3399_cru: implement dclk_vop0_frac and dclk_vop1_frac

add RK3399 DisplayPort clocks

add RK3399 eDP clocks

fix copy/paste error in mux_pll_src_cpll_gpll_ppll_parents[]

Add support for I2S clocks.

Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL
rates.

Add HDMI and VOP clocks

rk3399: add definition for the watchdog timer clock gate

The watchdog timer clock gate is a bit special because it's a secure
gate that can only be accessed from EL3. We still need a dummy gate
defi

rk3399: add definition for the watchdog timer clock gate

The watchdog timer clock gate is a bit special because it's a secure
gate that can only be accessed from EL3. We still need a dummy gate
definition for it so that dwcwdt(4) can infer the frequency via the
parent clock. The gate is enabled by default by U-Boot.

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rk3399_cru: add definitions for SPI clocks

Init bpll in a way that brings the big cluster's PLL out of "slow mode".
While here, fix a few typos in the cpul's rate table.

implement TSADC driver for rockchip RK3328 and RK3399. so far, only
tested on RK3399 but the RK3328 looks mostly the same and has a good
chance of working too.

add clock entries for "clk_tsadc" and

implement TSADC driver for rockchip RK3328 and RK3399. so far, only
tested on RK3399 but the RK3328 looks mostly the same and has a good
chance of working too.

add clock entries for "clk_tsadc" and "pclk_tsadc" to cru.

exports "CPU" and "GPU" temp sensors. these currently limited to 5
degC resolution but can be reduced to sub 1 degC resolution with some
interpolation.

todo list:

- handle setting various temp values
- add interpolation between the 5degC intervals in sample data
- handle DT trips/temp value defaults
- interrupts aren't triggered (test by lowering warn/crit values),
and once they work, make the interrupt do something
- test on RK3328, and port to other rockchips (will require moving
some part into per-chipset sections, such as code<->temp tables)


thanks to jmcneill for help.

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Fix aclk_emmc register offset, set RK_COMPOSITE_ROUND_DOWN for SD/EMMC clocks, and add a few more emmc clock nodes

Add eMMC clocks

Add clock information for RK3399 PCIe

Add support for RK3399 CPU clocks.

Add I2C clocks

Add support for Rockchip RK3399 SoC.