Some QED instructions are included in MIPS32 and MIPS64 instruction sets.
Update a few comments.

Tidy up NOP disassembly, handle "pause" as well.

add a "special3 offset" type of decode to ddb disasm so we see the
offsets properly decoded. add mips r6 "cache" insn.

avoid signed/unsigned compare and ufetch_32() for upcoming crash(8).

Fix value for SCE/SWE instructions.
Problem noticed by mrg@.

#define<tab>
Nuke trailing whitespace.

More instructions

Add a lot of missing mipsNNr2 instruction + cavium specific instructions.

Rework cavium support in preparation for MULTIPROCESSOR support

Change bcond/BCOND to regimm/REGIMM to better match the MIPS nomenclature.

emulate the special3 opcode LX (lwx, ldx, lhx, lbux) instructions.

Remove redundant lines.

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill Studl

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

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implement emulation of the "rdhwr" instruction for mips TLS.

Add disassemble code for DMT, DMF, MTH and MFH.

merge ktrace-lwp.

One defintion of OP_SYNC should be enough.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts

Overhaul the emulation facility. We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

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OP_BLTZAL was defined twice.

Add support for 3 QED special2 opcodes.

Add bi-endian support to mips locore, <mips/endian.h>, and mips_opcode.h.
Derived from a change request (PR port-mips/4277) from
Tsubai Masanari, (tsubai@iri.co.jp).

Merge in additions of missing MIPS-I opcodes, and r4000-in-32-bit mode
opcodes from the Pica port. Per Fogelstrom claims the latter are all
supposedly MIPS-II (r6000) instructions, rather than MIP

Merge in additions of missing MIPS-I opcodes, and r4000-in-32-bit mode
opcodes from the Pica port. Per Fogelstrom claims the latter are all
supposedly MIPS-II (r6000) instructions, rather than MIPS-III (R4000),
but we haven't checked to be sure. Are LL/SC really in MIPS-II?
CVS:: ----------------------------------------------------------------------

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new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids