Don't expose port-specific if _MODULE is defined.
Don't _MACHINE_CPU_H_, _<PORT>_CPU_H_

SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. T

SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

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Add some simple code to print out what the OFW thinks the cache
configuration of the machine is. Amusingly, the OFW on the pegasos is
dead wrong.

Bump CPU_MAXNUM to 8, because, thats probably a rea

Add some simple code to print out what the OFW thinks the cache
configuration of the machine is. Amusingly, the OFW on the pegasos is
dead wrong.

Bump CPU_MAXNUM to 8, because, thats probably a reasonable number for now.

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Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the v

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

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Put the declaration of cpu_softc and #include of sys/device.h inside
#ifdef _KERNEL to reduce the namespace pollution from proplib which
causes build failure in libexec/ld.elf_so.

implement device_register() for ofppc.
use ofcons_cnprobe().

Begin the task of splitting up the ofppc port into common code
and platform-specific code, similar to how the Alpha port is
split up.

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports.

Make all powerpc ports use a common Makefile.powerpc (except walnut)
Enforce -Wmissing-prototypes -Wstrict-prototypes for all ppc ports.
Split out macppc cpu support and make common to mpc6xx ports. Make
other mpc6xx ports use it. Add evcnts for mpc6xx traps.

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use _KERNEL_OPT

Remove the use of splimp() from the NetBSD kernel. splnet()
and only splnet() is allowed for the protection of data structures
used by network devices.

splimp -> splvm

Make sure everybody has an splvm() and equate it with splimp() (splimp()
is the historical name for this interrupt level, and the historical name
is going to go away in the near future).

Partial syscall cleanup, as per other ports.

Need to provide CACHELINESIZE in _STANDALONE environments, too.

Make need_resched() take a "struct cpu_info *" argument. This
causes gives a primitive form of processor affinity. Its use in
roundrobin() still needs some work.

Add spllock(). See spl(9) for details.

Make sure we provide splsched() as described in spl(9).

First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:

- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues)

First sweep at scheduler state cleanup. Collect MI scheduler
state into global and per-CPU scheduler state:

- Global state: sched_qs (run queues), sched_whichqs (bitmap
of non-empty run queues), sched_slpque (sleep queues).
NOTE: These may collectively move into a struct schedstate
at some point in the future.

- Per-CPU state, struct schedstate_percpu: spc_runtime
(time process on this CPU started running), spc_flags
(replaces struct proc's p_schedflags), and
spc_curpriority (usrpri of processes on this CPU).

- Every platform must now supply a struct cpu_info and
a curcpu() macro. Simplify existing cpu_info declarations
where appropriate.

- All references to per-CPU scheduler state now made through
curcpu(). NOTE: this will likely be adjusted in the future
after further changes to struct proc are made.

Tested on i386 and Alpha. Changes are mostly mechanical, but apologies
in advance if it doesn't compile on a particular platform.

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Define cpu_number() as discussed on tech-smp.

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old spl

Change the semantics of splsoftclock() to be like other spl*() functions,
that is priority is rasied. Add a new spllowersoftclock() to provide the
atomic drop-to-softclock semantics that the old splsoftclock() provided,
and update calls accordingly.

This fixes a problem with using the "rnd" pseudo-device from within
interrupt context to extract random data (e.g. from within the softnet
interrupt) where doing so would incorrectly unblock interrupts (causing
all sorts of lossage).

XXX 4 platforms do not have priority-raising capability: newsmips, sparc,
XXX sparc64, and VAX. This platforms still have this bug until their
XXX spl*() functions are fixed.

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Modify syncicache on PowerPC from an inline to a real function.
Support different cache line sizes with the same object code in userland.
While here, move the function to implementation name space.

asm -> __asm__, volatile -> __volatile

Definitions for machine_vec interface, from Wolfgang Solfrank.

PowerPC port