i915: Make intel_gtt_get prototype match Linux.

i915: ggtt

Update intel gtt API.

TODO: Find where the stolen memory base is in agp_i810.

Linux uses uint64 for these parameters now, so follow suit.

Call it intel_gtt_insert_sg_entries for expedience.

It uses a bus_dmamap, not a Linux scatterlist a.k.a. sg, but
otherwise it functions the same way and this avoids patching
upstream.

Pass cache-related flags through to the GTT on pre-SNB devices.

I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering

Pass cache-related flags through to the GTT on pre-SNB devices.

I had assumed for ages this would increase the amount of caching and
thereby increase the chance of stale caches leading to rendering
glitches. But apparently I was wrong, and failing to pass these
through was causing all sorts of problems!

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Make it build and boot on my test machines.

Screen blanks on boot on the Ivy Bridge system with

DRM error in cpt_serr_int_handler: PCH transcoder A FIFO underrun

But after that everything is OK

Make it build and boot on my test machines.

Screen blanks on boot on the Ivy Bridge system with

DRM error in cpt_serr_int_handler: PCH transcoder A FIFO underrun

But after that everything is OK. Appears to be an upstream problem.
To investigate...

I think there's a cache flushing issue somewhere -- there are little
display artefacts on my T60.

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Explain the fields of struct intel_gtt for future reference.

Merge riastradh-drm2 to HEAD.