Use evcount_percpu() with platform interrupt counters on octeon.

mips64, octeon, loonson: trigger deferred clock interrupts from splx(9)

As with powerpc, powerpc64, and riscv64, on mips64 platforms we need
to isolate the clock interrupt schedule from the MD clock

mips64, octeon, loonson: trigger deferred clock interrupts from splx(9)

As with powerpc, powerpc64, and riscv64, on mips64 platforms we need
to isolate the clock interrupt schedule from the MD clock interrupt
code. To do this, we need to stop deferring clock interrupt work
until the next tick and instead defer the work until we logically
unmask the clock interrupt from splx(9).

Add a boolean (ci_clock_deferred) to the cpu_info struct to note
whether we need to trigger the clock interrupt by hand, and then
do so from splx(9) by calling md_triggerclock().

Currently md_triggerclock is only ever set to cp0_trigger_int5(). The
routine takes great care to ensure that INT5 has fired or will fire
before returning.

There are some loongson machines that use glxclk instead of CP0. They
can be switched to use CP0 later.

With input and advice from visa@ and miod@.

Compiled and extensively tested by visa@ and miod@ on various octeon
and loongson machines. No issues seen on octeon machines. miod@ saw
some odd things on loongsoon, but suggests that all issues are
probably unrelated to this patch.

Link: https://marc.info/?l=openbsd-tech&m=165929192702632&w=2

ok visa@, miod@

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Make it clearer where message "spurious interrupt" comes from.

Remember to detach the event counter when disestablishing
an interrupt handler.

Replace a hand-rolled linked list with SLIST.

Let each interrupt controller driver choose how to implement
intr_barrier(9).

With this change, the barrier should finally work properly with
cnmac(4) interrupts that have been assigned to secondary

Let each interrupt controller driver choose how to implement
intr_barrier(9).

With this change, the barrier should finally work properly with
cnmac(4) interrupts that have been assigned to secondary cores.

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Include header <sys/evcount.h> where event counters are used, so that
header <machine/intr.h> can eventually stop including it on octeon.

Use a locally defined intrhand in octciu.c to ease future changes.

Fix the balancing of work queue interrupts.

The value of `ncpusfound' no longer reflects the number of cores that
will be utilized by the kernel; it can be larger if secondary cores
have not been en

Fix the balancing of work queue interrupts.

The value of `ncpusfound' no longer reflects the number of cores that
will be utilized by the kernel; it can be larger if secondary cores
have not been enabled by the firmware. This can lead to incorrect
assignment of work queue interrupts, making certain cnmac(4) ports
unable to receive packets. This is a regression introduced in r1.108 of
octeon/machdep.c.

Correct the problem by using `ncpus' for the balancing. All secondary
cores have been attached and the value is final by the time work queue
interrupt handlers are set up.

Network issue reported by krw@

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Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
remo

Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
removal of the explicit noreorder/reorder toggles from the C code.

With ci_ipl being volatile, drop mips_sync() calls that follow
the accesses of the variable. The sync is redundant as a compiler
barrier. In addition, the MIPS64 CPU designs should not need the
sync for pipeline or write buffer control. According to miod@,
the use of the instruction is a carryover from code targeting
early MIPS designs that lack tight integration with the cache
and write buffer.

Discussed with and testing help from miod@.
Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000,
R4400, R8000, R10000 and R16000.

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Always lock the kernel lock with non-MP-safe interrupt handlers.

Suggested by kettenis@

Fix a stupid typo.

Assign each cnmac(4) port its own input work group, and assign
the interrupt processing of each work group to one of the available
CPUs. This enables some parallelism in the early stages of packet Rx.

Add handling for the third interrupt summary vector,
needed by upcoming work.

Get cpuid from `ci' to avoid an extra function call.

Reorganize separate configuration fields into per-CPU structs
to compact the data indexing. This additionally improves the cache
locality of the data.

Fix function name in panic message.

Use a consistent naming for fdt attach arguments.

Split octeon interrupt code into a glue layer and a CIU driver.
This makes possible to add drivers for other interrupt controllers
on the platform.

The glue layer has been derived from arm64/armv7.