Implement execute-only mappings by using the Virtual Page Class Key
Protection mechanism provided by modern POWER CPUs. This is implemented
in a way data allows us to use the Data Address Compare me

Implement execute-only mappings by using the Virtual Page Class Key
Protection mechanism provided by modern POWER CPUs. This is implemented
in a way data allows us to use the Data Address Compare mechanism that
was available on older versions of the architecture if we ever add support
for these older CPUs (e.g. the PowerPC 970 aka G5).

Special thanks to gkoehler@ for spotting the bug in my initial
implementation that made this not work at all.

ok deraadt@, gkoehler@

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Enter power-saving mode on POWER9 (ISA v3)

When opal(4) attaches, look in the device tree for a psscr value. In
cpu_idle_cycle(), use this psscr value and the stop instruction to
wait for the next

Enter power-saving mode on POWER9 (ISA v3)

When opal(4) attaches, look in the device tree for a psscr value. In
cpu_idle_cycle(), use this psscr value and the stop instruction to
wait for the next interrupt. In mp kernels, cpu_unidle() now sends an
interrupt. In "sysctl hw.sensors", the power and temperature sensors
from opalsens(4) may show lower values.

The cpu may exit stop at the system reset vector after losing user
registers. If so, restore some registers. For now, ignore deeper
stop states that would lose hypervisor registers.

Our mp kernel uses only the first hardware thread of each core. Take
the extra threads from the firmware and stop them forever; this may
switch the core from SMT4 to single-thread mode and increase
performance.

partly by kettenis@, ok kettenis@

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Clear FSCR register. This gives us a sane default state where all facilities
are disabled by default on all CPUs.

Add support for POWER8 (and maybe earlier) CPUs. Not sure if this works on
real hardware, but it gets the kernel booting on QEMU emulating a POWER8
CPU so it's a step in the right direction.

This e

Add support for POWER8 (and maybe earlier) CPUs. Not sure if this works on
real hardware, but it gets the kernel booting on QEMU emulating a POWER8
CPU so it's a step in the right direction.

This establishes a way to distinguish CPU features based on the AT_HWCAP
and AT_HWCAP2 features documented in the ELF ABI. Also use this to
determine the availability of the DARN instruction instead of keying of
the processor model.

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Add hw.cpuspeed and hw.setperf

Get the list of Pstates from OPAL, and use special registers to
request a Pstate or check the current Pstate. The turbo Pstates are
higher than the cpu's nominal spee

Add hw.cpuspeed and hw.setperf

Get the list of Pstates from OPAL, and use special registers to
request a Pstate or check the current Pstate. The turbo Pstates are
higher than the cpu's nominal speed, but the OCC's firmware should
throttle down the cpu if it would overheat.

ok kettenis@

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Add sync().

Print CPU name and cache info in the same way as we do on arm64.

Add mtdec().

mainbus(4) and cpu(4).

Bootstrap a kernel pmap and enable translations.

Add some very simple trap handling.