Fix some spelling.

Input and ok jmc@, jsg@

Recognize the T-Head PLIC implementation.

ok jca@

riscv64: trigger deferred timer interrupts from splx(9)

In order to move riscv64 to a machine-independent clock interrupt
subsystem, the riscv64 clock interrupt code needs to function without
any sp

riscv64: trigger deferred timer interrupts from splx(9)

In order to move riscv64 to a machine-independent clock interrupt
subsystem, the riscv64 clock interrupt code needs to function without
any specific knowledge of the clock interrupt schedule.

The easiest way to achieve this (as we just did with powerpc and
powerpc64) is, if the timer interrupt fires while the CPU is at or
above IPL_CLOCK, defer clock interrupt work until the the timer
interrupt is logically unmasked in splx(9).

In particular, trigger the timer interrupt from plic_setipl() so the
interrupt, if any, is pending before we handle soft interrupts.

Because we're no longer deferring work until the next tick, we don't
need to count pending statclock ticks in struct cpu_info.

kettenis@ notes that the timer triggering code should be refactored
into more generic code when we add support for a non-plic(4) riscv64
machine.

Graciously fixed, compiled, and tested by jca@.

Link: https://marc.info/?l=openbsd-tech&m=165931635410276&w=2

ok kettenis@

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constify struct cfattach

plic: Fix cpuid handling

Make `cpu' signed so that the possible return value -1 from
plic_get_cpuid() gets handled correctly in the (cpu < 0) condition.
This prevents plic_attach() from updating sc_

plic: Fix cpuid handling

Make `cpu' signed so that the possible return value -1 from
plic_get_cpuid() gets handled correctly in the (cpu < 0) condition.
This prevents plic_attach() from updating sc_contexts[] out of bounds.

When plic_get_cpuid() returns -1, ignore the entry and continue
processing. The error is not fatal. It is normal that secondary CPUs
are not found when running a non-MULTIPROCESSOR kernel on
a multiprocessor machine.

OK kettenis@

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Don't use != 0 to check whether a pointer is non-NULL.

Bring riscv64 intr.c code in sync with arm64. This brings us:

- MSI support
- Interfaces to route interrupts to specific CPUs
- Proper interrupt barriers
- s/riscv_intr_handler/machine_intr_handler

Bring riscv64 intr.c code in sync with arm64. This brings us:

- MSI support
- Interfaces to route interrupts to specific CPUs
- Proper interrupt barriers
- s/riscv_intr_handler/machine_intr_handler/

ok mlarkin@

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Use intr_enable()/int_disable()/intr_restore() instead of
enable_interrupts()/disable_interrupts()/restore_interrupts() and remove
the latter interfaces.

ok mlarkin@, drahn@

Run handlers with interrupts enabled.

ok jsg@

add OpenBSD rcs ids

more whitespace cleanups

whitespace cleanup

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@g

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

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