The RISC-V architecture specification says that memory read/writes are
not ordered with respect to mmio read/writes. This appears to happen on
T-Head C920 cores as I'm seeing interrupts being enable

The RISC-V architecture specification says that memory read/writes are
not ordered with respect to mmio read/writes. This appears to happen on
T-Head C920 cores as I'm seeing interrupts being enabled before the lock
is released in mtx_leave() despite program order releasing the lock
before enabling interrupts. This is fixed by adding the necessary fences
in more or less the same places where Linux uses them.

ok patrick@, jca@

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Avoid doing cache flush/invalidate operations for DMA memory allocated with
the BUS_DMA_COHERENT flag.

ok miod@

add OpenBSD rcs ids

use fence iorw,iorw for bus_space_barrier()

ok kettenis@

Sync with arm64 version fixing bugs in some of the more obscure bus_space(9)
functions.

ok patrick@

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@g

Initial import of OpenBSD/riscv64

This work is based on the effort:
https://www.openbsd.org/papers/Porting_OpenBSD_to_RISCV_FinalReport.pdf
"Porting OpenBSD to RISC-V ISA"
by
Brian Bamsch <bbamsch@google.com>
Wenyan He <wenyan.he@sjsu.edu>
Mars Li <mengshi.li.mars@gmail.com>
Shivam Waghela <shivamwaghela@gmail.com>

With additional work by Dale Rahn <drahn@openbsd.org>

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