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9622c697 |
| 31-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add gvec compare with immediate and scalar operand
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loong
tcg: Add gvec compare with immediate and scalar operand
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230831030904.1194667-2-richard.henderson@linaro.org>
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#
9622c697 |
| 31-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add gvec compare with immediate and scalar operand
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loong
tcg: Add gvec compare with immediate and scalar operand
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230831030904.1194667-2-richard.henderson@linaro.org>
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Revision tags: v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
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#
76f9d6ad |
| 13-Jul-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult to tell when those changes have been
tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128
We adjust CONFIG_ATOMIC128 and CONFIG_CMPXCHG128 with CONFIG_ATOMIC128_OPT in atomic128.h. It is difficult to tell when those changes have been applied with the ifdef we must use with CONFIG_CMPXCHG128. So instead use HAVE_CMPXCHG128, which triggers -Werror-undef when the proper header has not been included.
Improves tcg_gen_atomic_cmpxchg_i128 for s390x host, which requires CONFIG_ATOMIC128_OPT. Without this we fall back to EXCP_ATOMIC to single-step 128-bit atomics, which is slow enough to cause some tests to time out.
Reported-by: Thomas Huth <thuth@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3 |
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#
fbea7a40 |
| 20-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu
With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pair
accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu
With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions.
The only use of the functions with explicit endianness was in target/sparc64, and that was only to satisfy the assert: the correct endianness is already built into memop.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2 |
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#
ddfdd417 |
| 28-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Widen helper_atomic_* addresses to uint64_t
Always pass the target address as uint64_t.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@li
tcg: Widen helper_atomic_* addresses to uint64_t
Always pass the target address as uint64_t.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0-rc1 |
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#
e570597a |
| 15-Mar-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
Always pass the target address as uint64_t.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderso
tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
Always pass the target address as uint64_t.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0-rc0 |
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#
35c653c4 |
| 15-Feb-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add 128-bit guest memory primitives
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4221aa4a |
| 28-Apr-2023 |
Nazar Kazakov <nazar.kazakov@codethink.co.uk> |
tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Message-Id: <2023042814
tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> [rth: Split out of larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4221aa4a |
| 28-Apr-2023 |
Nazar Kazakov <nazar.kazakov@codethink.co.uk> |
tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Message-Id: <2023042814
tcg: Add tcg_gen_gvec_andcs
Add tcg expander and helper functions for and-compliment vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> [rth: Split out of larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
123ae568 |
| 08-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add tcg_gen_{non}atomic_cmpxchg_i128
This will allow targets to avoid rolling their own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.or
tcg: Add tcg_gen_{non}atomic_cmpxchg_i128
This will allow targets to avoid rolling their own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
123ae568 |
| 08-Nov-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add tcg_gen_{non}atomic_cmpxchg_i128
This will allow targets to avoid rolling their own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.or
tcg: Add tcg_gen_{non}atomic_cmpxchg_i128
This will allow targets to avoid rolling their own.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0, v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0 |
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#
e28a8664 |
| 16-Jul-2021 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Standardize atomic helpers on softmmu api
Reduce the amount of code duplication by always passing the TCGMemOpIdx argument to helper_atomic_*. This is not currently used for user-only, b
accel/tcg: Standardize atomic helpers on softmmu api
Reduce the amount of code duplication by always passing the TCGMemOpIdx argument to helper_atomic_*. This is not currently used for user-only, but it's easy to ignore.
Tested-by: Cole Robinson <crobinso@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0, v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0 |
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#
db0c51a3 |
| 28-Oct-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Introduce tcg_splitwx_to_{rx,rw}
Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour.
Begin using the
tcg: Introduce tcg_splitwx_to_{rx,rw}
Add two helper functions, using a global variable to hold the displacement. The displacement is currently always 0, so no change in behaviour.
Begin using the functions in tcg common code only.
Reviewed-by: Joelle van Dyne <j@getutm.app> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
6d3ef048 |
| 15-Dec-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Use memset for large vector byte replication
In f47db80cc07, we handled odd-sized tail clearing for the case of hosts that have vector operations, but did not handle the case of hosts that do n
tcg: Use memset for large vector byte replication
In f47db80cc07, we handled odd-sized tail clearing for the case of hosts that have vector operations, but did not handle the case of hosts that do not have vector ops.
This was ok until e2e7168a214b, which changed the encoding of simd_desc such that the odd sizes are impossible.
Add memset as a tcg helper, and use that for all out-of-line byte stores to vectors. This includes, but is not limited to, the tail clearing operation in question.
Cc: qemu-stable@nongnu.org Buglink: https://bugs.launchpad.net/bugs/1907817 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0, v4.2.1, v5.0.0, v5.0.0-rc4 |
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#
5d0ceda9 |
| 20-Apr-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Implement gvec support for rotate by vector
No host backend support yet, but the interfaces for rotlv and rotrv are in place.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: R
tcg: Implement gvec support for rotate by vector
No host backend support yet, but the interfaces for rotlv and rotrv are in place.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Drop the generic expansion from rot to shift; we can do better for each backend, and then this code becomes unused.
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#
b0f7e744 |
| 20-Apr-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Implement gvec support for rotate by immediate
No host backend support yet, but the interfaces for rotli are in place. Canonicalize immediate rotate to the left, based on a survey of architect
tcg: Implement gvec support for rotate by immediate
No host backend support yet, but the interfaces for rotli are in place. Canonicalize immediate rotate to the left, based on a survey of architectures, but provide both left and right shift interfaces to the translators.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v5.0.0-rc3, v5.0.0-rc2, v5.0.0-rc1, v5.0.0-rc0, v4.2.0, v4.2.0-rc5, v4.2.0-rc4, v4.2.0-rc3, v4.2.0-rc2, v4.1.1, v4.2.0-rc1, v4.2.0-rc0, v4.0.1, v3.1.1.1, v4.1.0, v4.1.0-rc5, v4.1.0-rc4, v3.1.1, v4.1.0-rc3, v4.1.0-rc2, v4.1.0-rc1, v4.1.0-rc0 |
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#
38dc1294 |
| 30-Apr-2019 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add support for vector bitwise select
This operation performs d = (b & a) | (c & ~a), and is present on a majority of host vector units. Include gvec expanders.
Signed-off-by: Richard Henders
tcg: Add support for vector bitwise select
This operation performs d = (b & a) | (c & ~a), and is present on a majority of host vector units. Include gvec expanders.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v4.0.0 |
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#
bcefc902 |
| 17-Apr-2019 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add support for vector absolute value
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v4.0.0-rc4 |
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#
5ee5c14c |
| 14-Apr-2019 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add gvec expanders for variable shift
The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway,
tcg: Add gvec expanders for variable shift
The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v3.0.1, v4.0.0-rc3, v4.0.0-rc2, v4.0.0-rc1, v4.0.0-rc0 |
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#
dd0a0fcd |
| 18-Dec-2018 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add opcodes for vector minmax arithmetic
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
f550805d |
| 17-Dec-2018 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add gvec expanders for nand, nor, eqv
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, v3.0.0, v3.0.0-rc4, v2.12.1, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, v3.0.0-rc0, v2.11.2 |
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#
5507c2bf |
| 10-May-2018 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Introduce atomic helpers for integer min/max
Given that this atomic operation will be used by both risc-v and aarch64, let's not duplicate code across the two targets.
Reviewed-by: Peter Mayde
tcg: Introduce atomic helpers for integer min/max
Given that this atomic operation will be used by both risc-v and aarch64, let's not duplicate code across the two targets.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v2.12.0, v2.12.0-rc4, v2.12.0-rc3, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, v2.11.1 |
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#
22fc3527 |
| 21-Dec-2017 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add generic vector helpers with a scalar operand
Use dup to convert a non-constant scalar to a third vector.
Add addition, multiplication, and logical operations with an immediate. Add additio
tcg: Add generic vector helpers with a scalar operand
Use dup to convert a non-constant scalar to a third vector.
Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar operand comes first.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v2.10.2 |
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f49b12c6 |
| 14-Dec-2017 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add generic helpers for saturating arithmetic
No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive.
Review
tcg: Add generic helpers for saturating arithmetic
No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v2.11.0, v2.11.0-rc5, v2.11.0-rc4, v2.11.0-rc3, v2.11.0-rc2 |
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#
3774030a |
| 21-Nov-2017 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Add generic vector ops for multiplication
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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