#
03935f92 |
| 23-May-2024 |
Dorjoy Chowdhury <dorjoychy111@gmail.com> |
hw/arm/npcm7xx: remove setting of mp-affinity
The value of the mp-affinity property being set in npcm7xx_realize is always the same as the default value it would have when arm_cpu_realizefn is calle
hw/arm/npcm7xx: remove setting of mp-affinity
The value of the mp-affinity property being set in npcm7xx_realize is always the same as the default value it would have when arm_cpu_realizefn is called if the property is not set here. So there is no need to set the property value in npcm7xx_realize function.
Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240504141733.14813-1-dorjoychy111@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.2.4, v8.2.3, v7.2.11, v9.0.0 |
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#
eb656a60 |
| 22-Apr-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
Use little endian for derivative OTP fuse key.
Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Sug
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
Use little endian for derivative OTP fuse key.
Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240422125813.1403-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.2.4, v8.2.3, v7.2.11, v9.0.0 |
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#
eb656a60 |
| 22-Apr-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
Use little endian for derivative OTP fuse key.
Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Sug
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
Use little endian for derivative OTP fuse key.
Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240422125813.1403-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v9.0.0-rc4, v9.0.0-rc3, v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10 |
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#
243f865a |
| 06-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
The patchset adding the GMAC ethernet to this SoC crossed in the mail with the patchset cleaning up the NIC handling. When we create
hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules
The patchset adding the GMAC ethernet to this SoC crossed in the mail with the patchset cleaning up the NIC handling. When we create the GMAC modules we must call qemu_configure_nic_device() so that the user has the opportunity to use the -nic commandline option to create a network backend and connect it to the GMACs.
Add the missing call.
Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Message-id: 20240206171231.396392-2-peter.maydell@linaro.org
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Revision tags: v8.2.1, v8.1.5, v7.2.9, v8.1.4, v7.2.8, v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
707a42e2 |
| 23-Oct-2023 |
David Woodhouse <dwmw@amazon.co.uk> |
hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases
Also update the test to specify which device to attach the test socket to, and remove the comment lamenting the fact that we
hw/arm/npcm7xx: use qemu_configure_nic_device, allow emc0/emc1 as aliases
Also update the test to specify which device to attach the test socket to, and remove the comment lamenting the fact that we can't do so.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
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#
21e5326a |
| 31-Jan-2024 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Add GMAC devices to NPCM7XX SoC
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Review
hw/arm: Add GMAC devices to NPCM7XX SoC
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-3-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d780d056 |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handle
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file.
File list to include the new header generated using:
$ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
750245ed |
| 18-Jan-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Rename arm_cpu_mp_affinity
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson
target/arm: Rename arm_cpu_mp_affinity
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d780d056 |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handle
target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file.
File list to include the new header generated using:
$ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)'
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
750245ed |
| 18-Jan-2024 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Rename arm_cpu_mp_affinity
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson
target/arm: Rename arm_cpu_mp_affinity
Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
4d120d7d |
| 08-Feb-2023 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
4d120d7d |
| 08-Feb-2023 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
4d120d7d |
| 08-Feb-2023 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
4d120d7d |
| 08-Feb-2023 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
4d120d7d |
| 08-Feb-2023 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-
hw/arm: Attach PSPI module to NPCM7XX SoC
Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Titus Rwantare <titusr@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20230208235433.3989937-4-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0, v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
d6dc926e |
| 27-Jan-2022 |
Peter Maydell <peter.maydell@linaro.org> |
hw/arm/boot: Drop nb_cpus field from arm_boot_info
We use the arm_boot_info::nb_cpus field in only one place, and that place can easily get the number of CPUs locally rather than relying on the boar
hw/arm/boot: Drop nb_cpus field from arm_boot_info
We use the arm_boot_info::nb_cpus field in only one place, and that place can easily get the number of CPUs locally rather than relying on the board code to have set the field correctly. (At least one board, xlnx-versal-virt, does not set the field despite having more than one CPU.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20220127154639.2090164-16-peter.maydell@linaro.org
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Revision tags: v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1 |
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#
0a9df6cb |
| 08-Oct-2021 |
Shengtan Mao <stmao@google.com> |
hw/arm: Add Nuvoton SD module to board
Signed-off-by: Shengtan Mao <stmao@google.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Chris Rauer <
hw/arm: Add Nuvoton SD module to board
Signed-off-by: Shengtan Mao <stmao@google.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Chris Rauer <crauer@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20211008002628.1958285-3-wuhaotsh@google.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4 |
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#
ee86213a |
| 16-Apr-2021 |
Thomas Huth <thuth@redhat.com> |
Do not include exec/address-spaces.h if it's not really necessary
Stop including exec/address-spaces.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <202104
Do not include exec/address-spaces.h if it's not really necessary
Stop including exec/address-spaces.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0 |
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#
fc11115f |
| 11-Mar-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Add MFT device to NPCM7xx Soc
This patch adds the recently implemented MFT device to the NPCM7XX SoC file.
Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.
hw/arm: Add MFT device to NPCM7xx Soc
This patch adds the recently implemented MFT device to the NPCM7XX SoC file.
Reviewed-by: Doug Evans <dje@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210311180855.149764-4-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
77586436 |
| 18-Feb-2021 |
Doug Evans <dje@google.com> |
hw/arm: Add npcm7xx emc model
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemente
hw/arm: Add npcm7xx emc model
This is a 10/100 ethernet device that has several features. Only the ones needed by the Linux driver have been implemented. See npcm7xx_emc.c for a list of unimplemented features.
Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Doug Evans <dje@google.com> Message-id: 20210218212453.831406-3-dje@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
94e77879 |
| 10-Feb-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/i2c: Implement NPCM7XX SMBus Module Single Mode
This commit implements the single-byte mode of the SMBus.
Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus
hw/i2c: Implement NPCM7XX SMBus Module Single Mode
This commit implements the single-byte mode of the SMBus.
Each Nuvoton SoC has 16 System Management Bus (SMBus). These buses compliant with SMBus and I2C protocol.
This patch implements the single-byte mode of the SMBus. In this mode, the user sends or receives a byte each time. The SMBus device transmits it to the underlying i2c device and sends an interrupt back to the QEMU guest.
Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Message-id: 20210210220426.3577804-2-wuhaotsh@google.com Acked-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
377a3ba2 |
| 29-Jan-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/arm: Remove GPIO from unimplemented NPCM7XX
NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list.
Reviewed-by: Doug Evans<
hw/arm: Remove GPIO from unimplemented NPCM7XX
NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So we removed them from the unimplemented devices list.
Reviewed-by: Doug Evans<dje@google.com> Reviewed-by: Tyrong Ting<kfting@nuvoton.com> Signed-off-by: Hao Wu<wuhaotsh@google.com> Message-id: 20210129005845.416272-2-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
1e943c58 |
| 08-Jan-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/misc: Add a PWM module for NPCM7XX
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two identical PWM modules. Each module contains 4 PWM entries. Each PWM has two outputs: frequ
hw/misc: Add a PWM module for NPCM7XX
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two identical PWM modules. Each module contains 4 PWM entries. Each PWM has two outputs: frequency and duty_cycle. Both are computed using inputs from software side.
This module does not model detail pulse signals since it is expensive. It also does not model interrupts and watchdogs that are dependant on the detail models. The interfaces for these are left in the module so that anyone in need for these functionalities can implement on their own.
The user can read the duty cycle and frequency using qom-get command.
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-5-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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77c05b0b |
| 08-Jan-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/adc: Add an ADC module for NPCM7XX
The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores
hw/adc: Add an ADC module for NPCM7XX
The ADC is part of NPCM7XX Module. Its behavior is controled by the ADC_CON register. It converts one of the eight analog inputs into a digital input and stores it in the ADC_DATA register when enabled.
Users can alter input value by using qom-set QMP command.
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-4-wuhaotsh@google.com [PMM: Added missing hw/adc/trace.h file] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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0be12dc7 |
| 08-Jan-2021 |
Hao Wu <wuhaotsh@google.com> |
hw/timer: Refactor NPCM7XX Timer to use CLK clock
This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ.
Reviewed-by: Havard S
hw/timer: Refactor NPCM7XX Timer to use CLK clock
This patch makes NPCM7XX Timer to use a the timer clock generated by the CLK module instead of the magic number TIMER_REF_HZ.
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Hao Wu <wuhaotsh@google.com> Message-id: 20210108190945.949196-3-wuhaotsh@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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