Revision tags: v9.0.3, v8.2.7, v7.2.14, v9.1.0 |
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#
737cb2f3 |
| 30-Aug-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw/gpio/aspeed_gpio: Avoid shift into sign bit
In aspeed_gpio_update() we calculate "mask = 1 << gpio", where gpio can be between 0 and 31. Coverity complains about this because 1 << 31 won't fit in
hw/gpio/aspeed_gpio: Avoid shift into sign bit
In aspeed_gpio_update() we calculate "mask = 1 << gpio", where gpio can be between 0 and 31. Coverity complains about this because 1 << 31 won't fit in a signed integer.
For QEMU this isn't an error because we enable -fwrapv, but we can keep Coverity happy by doing the shift on unsigned numbers.
Resolves: Coverity CID 1547742 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com>
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e3d08143 |
| 13-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/device-reset.cocci \ --keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
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Revision tags: v9.1.0-rc4, v9.1.0-rc3, v9.1.0-rc2, v9.1.0-rc1, v9.1.0-rc0, v9.0.2, v8.2.6, v7.2.13 |
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#
87511bb8 |
| 20-Jun-2024 |
Zheyu Ma <zheyuma97@gmail.com> |
hw/gpio/aspeed: Add reg_table_count to AspeedGPIOClass
ASan detected a global-buffer-overflow error in the aspeed_gpio_read() function. This issue occurred when reading beyond the bounds of the reg_
hw/gpio/aspeed: Add reg_table_count to AspeedGPIOClass
ASan detected a global-buffer-overflow error in the aspeed_gpio_read() function. This issue occurred when reading beyond the bounds of the reg_table.
To enhance the safety and maintainability of the Aspeed GPIO code, this commit introduces a reg_table_count member to the AspeedGPIOClass structure. This change ensures that the size of the GPIO register table is explicitly tracked and initialized, reducing the risk of errors if new register tables are introduced in the future.
Reproducer: cat << EOF | qemu-system-aarch64 -display none \ -machine accel=qtest, -m 512M -machine ast1030-evb -qtest stdio readq 0x7e780272 EOF
ASAN log indicating the issue: ==2602930==ERROR: AddressSanitizer: global-buffer-overflow on address 0x55a5da29e128 at pc 0x55a5d700dc62 bp 0x7fff096c4e90 sp 0x7fff096c4e88 READ of size 2 at 0x55a5da29e128 thread T0 #0 0x55a5d700dc61 in aspeed_gpio_read hw/gpio/aspeed_gpio.c:564:14 #1 0x55a5d933f3ab in memory_region_read_accessor system/memory.c:445:11 #2 0x55a5d92fba40 in access_with_adjusted_size system/memory.c:573:18 #3 0x55a5d92f842c in memory_region_dispatch_read1 system/memory.c:1426:16 #4 0x55a5d92f7b68 in memory_region_dispatch_read system/memory.c:1459:9 #5 0x55a5d9376ad1 in flatview_read_continue_step system/physmem.c:2836:18 #6 0x55a5d9376399 in flatview_read_continue system/physmem.c:2877:19 #7 0x55a5d93775b8 in flatview_read system/physmem.c:2907:12
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2355 Signed-off-by: Zheyu Ma <zheyuma97@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Revision tags: v9.0.1, v8.2.5, v7.2.12, v8.2.4, v8.2.3, v7.2.11, v9.0.0, v9.0.0-rc4, v9.0.0-rc3, v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9, v8.1.4, v7.2.8 |
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#
3b9e779b |
| 21-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
hw/gpio: Constify VMState
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-29-richard.henderson@linaro.org>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0, v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
1f30db92 |
| 14-Jul-2022 |
Peter Delevoryas <peter@pjd.dev> |
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin value
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin values, and the QOM property setter should only be permitted to modify input pins.
This change also updates the gpio input pin test to match this expectation.
Andrew suggested this particularly refactoring here:
https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612@www.fastmail.com/
Suggested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Peter Delevoryas <peter@pjd.dev> Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220712023219.41065-3-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0, v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
1f30db92 |
| 14-Jul-2022 |
Peter Delevoryas <peter@pjd.dev> |
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin value
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin values, and the QOM property setter should only be permitted to modify input pins.
This change also updates the gpio input pin test to match this expectation.
Andrew suggested this particularly refactoring here:
https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612@www.fastmail.com/
Suggested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Peter Delevoryas <peter@pjd.dev> Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220712023219.41065-3-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0, v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
|
#
1f30db92 |
| 14-Jul-2022 |
Peter Delevoryas <peter@pjd.dev> |
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin value
hw/gpio/aspeed: Don't let guests modify input pins
Up until now, guests could modify input pins by overwriting the data value register. The guest OS should only be allowed to modify output pin values, and the QOM property setter should only be permitted to modify input pins.
This change also updates the gpio input pin test to match this expectation.
Andrew suggested this particularly refactoring here:
https://lore.kernel.org/qemu-devel/23523aa1-ba81-412b-92cc-8174faba3612@www.fastmail.com/
Suggested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Peter Delevoryas <peter@pjd.dev> Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220712023219.41065-3-peter@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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554c2945 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64 2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Mess
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64 2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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247c0029 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@ka
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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17075ef2 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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7b1d21a8 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-I
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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554c2945 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64 2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Mess
hw/gpio: replace HWADDR_PRIx with PRIx64
1. replace HWADDR_PRIx with PRIx64 2. fix indent issue
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
247c0029 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@ka
hw/gpio support GPIO index mode for write operation.
It did not support GPIO index mode for read operation.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
17075ef2 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6
hw/gpio: Add ASPEED GPIO model for AST1030
AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
7b1d21a8 |
| 25-May-2022 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-I
hw/gpio Add GPIO read/write trace event.
Add GPIO read/write trace event for aspeed model.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
2ec06378 |
| 02-May-2022 |
Peter Delevoryas <pdel@fb.com> |
hw/gpio/aspeed_gpio: Fix QOM pin property
I was setting gpioV4-7 to "1110" using the QOM pin property handler and noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.
(qemu) qo
hw/gpio/aspeed_gpio: Fix QOM pin property
I was setting gpioV4-7 to "1110" using the QOM pin property handler and noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too.
(qemu) qom-set /machine/soc/gpio gpioV4 true (qemu) qom-set /machine/soc/gpio gpioV5 true (qemu) qom-set /machine/soc/gpio gpioV6 true (qemu) qom-get /machine/soc/gpio gpioV4 true (qemu) qom-set /machine/soc/gpio gpioV7 false (qemu) qom-get /machine/soc/gpio gpioV4 false
An expression in aspeed_gpio_set_pin_level was using a logical NOT operator instead of a bitwise NOT operator:
value &= !pin_mask;
The original author probably intended to make a bitwise NOT expression "~", but mistakenly used a logical NOT operator "!" instead. Some programming languages like Rust use "!" for both purposes.
Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220502080827.244815-1-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
46179776 |
| 08-Mar-2022 |
Andrew Jeffery <andrew@aj.id.au> |
hw: aspeed_gpio: Cleanup stray semicolon after switch
Not sure how that got there.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20220207150409.358888-2-andrew@aj.id.au> Signed-off-b
hw: aspeed_gpio: Cleanup stray semicolon after switch
Not sure how that got there.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20220207150409.358888-2-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1 |
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#
87bd33e8 |
| 12-Oct-2021 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed_gpio: Fix GPIO array indexing
The gpio array is declared as a dense array:
qemu_irq gpios[ASPEED_GPIO_NR_PINS];
(AST2500 has 228, AST2400 has 216, AST2600 has 208)
However, this arra
hw: aspeed_gpio: Fix GPIO array indexing
The gpio array is declared as a dense array:
qemu_irq gpios[ASPEED_GPIO_NR_PINS];
(AST2500 has 228, AST2400 has 216, AST2600 has 208)
However, this array is used like a matrix of GPIO sets (e.g. gpio[NR_SETS][NR_PINS_PER_SET] = gpio[8][32])
size_t offset = set * GPIOS_PER_SET + gpio; qemu_set_irq(s->gpios[offset], !!(new & mask));
This can result in an out-of-bounds access to "s->gpios" because the gpio sets do _not_ have the same length. Some of the groups (e.g. GPIOAB) only have 4 pins. 228 != 8 * 32 == 256.
To fix this, I converted the gpio array from dense to sparse, to that match both the hardware layout and this existing indexing code.
Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20211008033501.934729-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
9fffe140 |
| 12-Oct-2021 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed_gpio: Fix pin I/O type declarations
Some of the pin declarations in the Aspeed GPIO module were incorrect, probably because of confusion over which bits in the input and output uint32_t's
hw: aspeed_gpio: Fix pin I/O type declarations
Some of the pin declarations in the Aspeed GPIO module were incorrect, probably because of confusion over which bits in the input and output uint32_t's correspond to which groups in the label array. Since the uint32_t literals are in big endian, it's sort of the opposite of what would be intuitive. The least significant bit in ast2500_set_props[6] corresponds to GPIOY0, not GPIOAB7.
GPIOxx indicates input and output capabilities, GPIxx indicates only input, GPOxx indicates only output.
AST2500: - Previously had GPIW0..GPIW7 and GPIX0..GPIX7, that's correct. - Previously had GPIOY0..GPIOY3, should have been GPIOY0..GPIOY7. - Previously had GPIOAB0..GPIOAB3 and GPIAB4..GPIAB7, should only have been GPIOAB0..GPIOAB3.
AST2600: - GPIOT0..GPIOT7 should have been GPIT0..GPIT7. - GPIOU0..GPIOU7 should have been GPIU0..GPIU7. - GPIW0..GPIW7 should have been GPIOW0..GPIOW7. - GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled.
Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Fixes: 36d737ee82b2972167e ("hw/gpio: Add in AST2600 specific implementation") Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Message-Id: <20210928032456.3192603-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
98edb134 |
| 20-Sep-2021 |
Joel Stanley <joel@jms.id.au> |
hw: aspeed_gpio: Clarify GPIO controller name
There are two GPIO controllers in the ast2600; one is 3.3V and the other is 1.8V.
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gu
hw: aspeed_gpio: Clarify GPIO controller name
There are two GPIO controllers in the ast2600; one is 3.3V and the other is 1.8V.
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210713065854.134634-4-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
64e5758b |
| 20-Sep-2021 |
Joel Stanley <joel@jms.id.au> |
hw: aspeed_gpio: Simplify 1.8V defines
There's no need to define the registers relative to the 0x800 offset where the controller is mapped, as the device is instantiated as it's own model at the cor
hw: aspeed_gpio: Simplify 1.8V defines
There's no need to define the registers relative to the 0x800 offset where the controller is mapped, as the device is instantiated as it's own model at the correct memory address.
Simplify the defines and remove the offset to save future confusion.
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210713065854.134634-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0 |
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e229a179 |
| 13-Jul-2021 |
Joel Stanley <joel@jms.id.au> |
hw: aspeed_gpio: Fix memory size
The macro used to calculate the maximum memory size of the MMIO region had a mistake, causing all GPIO models to create a mapping of 0x9D8. The intent was to have it
hw: aspeed_gpio: Fix memory size
The macro used to calculate the maximum memory size of the MMIO region had a mistake, causing all GPIO models to create a mapping of 0x9D8. The intent was to have it be 0x9D8 - 0x800.
This extra size doesn't matter on ast2400 and ast2500, which have a 4KB region set aside for the GPIO controller.
On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the regions would overlap. Worse was the 1.8V controller would map over the top of the following peripheral, which happens to be the RTC.
The mmio region used by each device is a maximum of 2KB, so avoid the calculations and hard code this as the maximum.
Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20210713065854.134634-2-joel@jms.id.au [PMM: fix autocorrect error in commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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58519090 |
| 16-May-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
misc: Correct relative include path
Headers should be included from the 'include/' directory, not from the root directory.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin M
misc: Correct relative include path
Headers should be included from the 'include/' directory, not from the root directory.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210516205034.694788-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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bcfec376 |
| 08-May-2021 |
Michael Tokarev <mjt@tls.msk.ru> |
hw/gpio/aspeed: spelling fix (addtional)
Fixes: 36d737ee82b2972167e97901c5271ba3f904ba71 Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message
hw/gpio/aspeed: spelling fix (addtional)
Fixes: 36d737ee82b2972167e97901c5271ba3f904ba71 Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210508093615.411920-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0, v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0, v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0 |
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668f62ec |
| 07-Jul-2020 |
Markus Armbruster <armbru@redhat.com> |
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert
if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... }
to
if (!foo(..., errp)) { ... ... return ... }
where nothing else needs @err. Coccinelle script:
@rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) }
@rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) }
@depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err);
even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here.
The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
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