Lines Matching refs:ram_block3a_10
1944 cyclone_ram_block ram_block3a_10 instance
1978 ram_block3a_10.connectivity_checking = "OFF",
1979 ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
1980 ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
1981 ram_block3a_10.operation_mode = "dual_port",
1982 ram_block3a_10.port_a_address_width = 12,
1983 ram_block3a_10.port_a_data_width = 1,
1984 ram_block3a_10.port_a_first_address = 0,
1985 ram_block3a_10.port_a_first_bit_number = 10,
1986 ram_block3a_10.port_a_last_address = 4095,
1987 ram_block3a_10.port_a_logical_ram_depth = 4096,
1988 ram_block3a_10.port_a_logical_ram_width = 16,
1989 ram_block3a_10.port_b_address_clear = "none",
1990 ram_block3a_10.port_b_address_clock = "clock1",
1991 ram_block3a_10.port_b_address_width = 12,
1992 ram_block3a_10.port_b_data_out_clear = "none",
1993 ram_block3a_10.port_b_data_out_clock = "none",
1994 ram_block3a_10.port_b_data_width = 1,
1995 ram_block3a_10.port_b_first_address = 0,
1996 ram_block3a_10.port_b_first_bit_number = 10,
1997 ram_block3a_10.port_b_last_address = 4095,
1998 ram_block3a_10.port_b_logical_ram_depth = 4096,
1999 ram_block3a_10.port_b_logical_ram_width = 16,
2000 ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
2001 ram_block3a_10.ram_block_type = "auto",
2002 ram_block3a_10.lpm_type = "cyclone_ram_block";