Lines Matching defs:to
32 %11 = sext <8 x i16> %wide.masked.load to <8 x i32>
41 %17 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1)
50 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
58 ---
59 name: test
63 - { id: 0, class: rgpr, preferred-register: '' }
70 - { id: 7, class: gpr, preferred-register: '' }
77 - { id: 14, class: gpr, preferred-register: '' }
84 - { id: 21, class: gprnopc, preferred-register: '' }
92 - { id: 29, class: mqpr, preferred-register: '' }
96 - { id: 33, class: gprlr, preferred-register: '' }
100 - { reg: '$r0', virtual-reg: '%13' }
107 ; CHECK: liveins: $r0, $r1, $r2
116 ; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY [[t2MOVi]]
125 ; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]]
134 ; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3
141 …; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16…
150 ; CHECK: $r0 = COPY [[PHI5]]
159 t2CMPri %15, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr