1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+lob -run-pass=arm-mve-vpt-opts %s -verify-machineinstrs -o - | FileCheck %s 3 4--- | 5 6 define i32 @test(i16* nocapture readonly %x, i16* nocapture readonly %y, i32 %n) { 7 entry: 8 %cmp10 = icmp sgt i32 %n, 0 9 %0 = add i32 %n, 7 10 %1 = lshr i32 %0, 3 11 %2 = shl nuw i32 %1, 3 12 %3 = add i32 %2, -8 13 %4 = lshr i32 %3, 3 14 %5 = add nuw nsw i32 %4, 1 15 br i1 %cmp10, label %vector.ph, label %for.cond.cleanup 16 17 vector.ph: ; preds = %entry 18 %6 = call i32 @llvm.start.loop.iterations.i32(i32 %5) 19 br label %vector.body 20 21 vector.body: ; preds = %vector.body, %vector.ph 22 %lsr.iv3 = phi i16* [ %scevgep4, %vector.body ], [ %x, %vector.ph ] 23 %lsr.iv1 = phi i16* [ %scevgep, %vector.body ], [ %y, %vector.ph ] 24 %vec.phi = phi i32 [ 0, %vector.ph ], [ %16, %vector.body ] 25 %7 = phi i32 [ %6, %vector.ph ], [ %17, %vector.body ] 26 %8 = phi i32 [ %n, %vector.ph ], [ %10, %vector.body ] 27 %lsr.iv12 = bitcast i16* %lsr.iv1 to <8 x i16>* 28 %lsr.iv35 = bitcast i16* %lsr.iv3 to <8 x i16>* 29 %9 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %8) 30 %10 = sub i32 %8, 8 31 %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv35, i32 2, <8 x i1> %9, <8 x i16> undef) 32 %11 = sext <8 x i16> %wide.masked.load to <8 x i32> 33 %wide.masked.load13 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv12, i32 2, <8 x i1> %9, <8 x i16> undef) 34 %12 = sext <8 x i16> %wide.masked.load13 to <8 x i32> 35 %13 = mul nsw <8 x i32> %12, %11 36 %14 = select <8 x i1> %9, <8 x i32> %13, <8 x i32> zeroinitializer 37 %15 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %14) 38 %16 = add i32 %15, %vec.phi 39 %scevgep = getelementptr i16, i16* %lsr.iv1, i32 8 40 %scevgep4 = getelementptr i16, i16* %lsr.iv3, i32 8 41 %17 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1) 42 %18 = icmp ne i32 %17, 0 43 br i1 %18, label %vector.body, label %for.cond.cleanup 44 45 for.cond.cleanup: ; preds = %vector.body, %entry 46 %s.0.lcssa = phi i32 [ 0, %entry ], [ %16, %vector.body ] 47 ret i32 %s.0.lcssa 48 } 49 50 declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32) 51 declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>) 52 declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) 53 declare i32 @llvm.start.loop.iterations.i32(i32) 54 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) 55 declare <8 x i1> @llvm.arm.mve.vctp16(i32) 56 57... 58--- 59name: test 60alignment: 2 61tracksRegLiveness: true 62registers: 63 - { id: 0, class: rgpr, preferred-register: '' } 64 - { id: 1, class: gpr, preferred-register: '' } 65 - { id: 2, class: rgpr, preferred-register: '' } 66 - { id: 3, class: rgpr, preferred-register: '' } 67 - { id: 4, class: tgpreven, preferred-register: '' } 68 - { id: 5, class: gprlr, preferred-register: '' } 69 - { id: 6, class: rgpr, preferred-register: '' } 70 - { id: 7, class: gpr, preferred-register: '' } 71 - { id: 8, class: gpr, preferred-register: '' } 72 - { id: 9, class: gpr, preferred-register: '' } 73 - { id: 10, class: gpr, preferred-register: '' } 74 - { id: 11, class: gpr, preferred-register: '' } 75 - { id: 12, class: gpr, preferred-register: '' } 76 - { id: 13, class: gpr, preferred-register: '' } 77 - { id: 14, class: gpr, preferred-register: '' } 78 - { id: 15, class: gprnopc, preferred-register: '' } 79 - { id: 16, class: gpr, preferred-register: '' } 80 - { id: 17, class: rgpr, preferred-register: '' } 81 - { id: 18, class: rgpr, preferred-register: '' } 82 - { id: 19, class: rgpr, preferred-register: '' } 83 - { id: 20, class: rgpr, preferred-register: '' } 84 - { id: 21, class: gprnopc, preferred-register: '' } 85 - { id: 22, class: rgpr, preferred-register: '' } 86 - { id: 23, class: gpr, preferred-register: '' } 87 - { id: 24, class: gprlr, preferred-register: '' } 88 - { id: 25, class: rgpr, preferred-register: '' } 89 - { id: 26, class: vccr, preferred-register: '' } 90 - { id: 27, class: rgpr, preferred-register: '' } 91 - { id: 28, class: rgpr, preferred-register: '' } 92 - { id: 29, class: mqpr, preferred-register: '' } 93 - { id: 30, class: rgpr, preferred-register: '' } 94 - { id: 31, class: mqpr, preferred-register: '' } 95 - { id: 32, class: tgpreven, preferred-register: '' } 96 - { id: 33, class: gprlr, preferred-register: '' } 97 - { id: 34, class: gprlr, preferred-register: '' } 98 - { id: 35, class: gprnopc, preferred-register: '' } 99liveins: 100 - { reg: '$r0', virtual-reg: '%13' } 101 - { reg: '$r1', virtual-reg: '%14' } 102 - { reg: '$r2', virtual-reg: '%15' } 103body: | 104 ; CHECK-LABEL: name: test 105 ; CHECK: bb.0.entry: 106 ; CHECK: successors: %bb.2(0x50000000), %bb.1(0x30000000) 107 ; CHECK: liveins: $r0, $r1, $r2 108 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r2 109 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 110 ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r0 111 ; CHECK: t2CMPri [[COPY]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 112 ; CHECK: t2Bcc %bb.2, 10 /* CC::ge */, $cpsr 113 ; CHECK: bb.1: 114 ; CHECK: successors: %bb.4(0x80000000) 115 ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 116 ; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY [[t2MOVi]] 117 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg 118 ; CHECK: bb.2.vector.ph: 119 ; CHECK: successors: %bb.3(0x80000000) 120 ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 7, 14 /* CC::al */, $noreg, $noreg 121 ; CHECK: [[t2BICri:%[0-9]+]]:rgpr = t2BICri [[t2ADDri]], 7, 14 /* CC::al */, $noreg, $noreg 122 ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2BICri]], 8, 14 /* CC::al */, $noreg, $noreg 123 ; CHECK: [[t2MOVi1:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 124 ; CHECK: [[t2ADDrs:%[0-9]+]]:gprnopc = nuw nsw t2ADDrs [[t2MOVi1]], [[t2SUBri]], 27, 14 /* CC::al */, $noreg, $noreg 125 ; CHECK: [[COPY4:%[0-9]+]]:rgpr = COPY [[t2ADDrs]] 126 ; CHECK: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 127 ; CHECK: [[COPY5:%[0-9]+]]:gpr = COPY [[t2MOVi2]] 128 ; CHECK: [[COPY6:%[0-9]+]]:rgpr = COPY [[COPY]] 129 ; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]] 130 ; CHECK: bb.3.vector.body: 131 ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) 132 ; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3 133 ; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3 134 ; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3 135 ; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3 136 ; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3 137 ; CHECK: [[MVE_VCTP16_:%[0-9]+]]:vccr = MVE_VCTP16 [[PHI4]], 0, $noreg 138 ; CHECK: [[t2SUBri1:%[0-9]+]]:rgpr = t2SUBri [[PHI4]], 8, 14 /* CC::al */, $noreg, $noreg 139 ; CHECK: [[COPY7:%[0-9]+]]:gpr = COPY [[t2SUBri1]] 140 ; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI]], 16, 1, [[MVE_VCTP16_]] :: (load (s128) from %ir.lsr.iv35, align 2) 141 ; CHECK: [[MVE_VLDRHU16_post2:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post3:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[PHI1]], 16, 1, [[MVE_VCTP16_]] :: (load (s128) from %ir.lsr.iv12, align 2) 142 ; CHECK: [[MVE_VMLADAVas16_:%[0-9]+]]:tgpreven = MVE_VMLADAVas16 [[PHI2]], killed [[MVE_VLDRHU16_post3]], killed [[MVE_VLDRHU16_post1]], 1, [[MVE_VCTP16_]] 143 ; CHECK: [[COPY8:%[0-9]+]]:gpr = COPY [[MVE_VMLADAVas16_]] 144 ; CHECK: [[COPY9:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post2]] 145 ; CHECK: [[COPY10:%[0-9]+]]:gpr = COPY [[MVE_VLDRHU16_post]] 146 ; CHECK: [[t2LoopEndDec:%[0-9]+]]:gprlr = t2LoopEndDec [[PHI3]], %bb.3, implicit-def $cpsr 147 ; CHECK: t2B %bb.4, 14 /* CC::al */, $noreg 148 ; CHECK: bb.4.for.cond.cleanup: 149 ; CHECK: [[PHI5:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.1, [[COPY8]], %bb.3 150 ; CHECK: $r0 = COPY [[PHI5]] 151 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 152 bb.0.entry: 153 successors: %bb.1(0x50000000), %bb.4(0x30000000) 154 liveins: $r0, $r1, $r2 155 156 %15:gprnopc = COPY $r2 157 %14:gpr = COPY $r1 158 %13:gpr = COPY $r0 159 t2CMPri %15, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 160 t2Bcc %bb.1, 10 /* CC::ge */, $cpsr 161 162 bb.4: 163 successors: %bb.3(0x80000000) 164 165 %22:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 166 %16:gpr = COPY %22 167 t2B %bb.3, 14 /* CC::al */, $noreg 168 169 bb.1.vector.ph: 170 successors: %bb.2(0x80000000) 171 172 %17:rgpr = t2ADDri %15, 7, 14 /* CC::al */, $noreg, $noreg 173 %18:rgpr = t2BICri %17, 7, 14 /* CC::al */, $noreg, $noreg 174 %19:rgpr = t2SUBri %18, 8, 14 /* CC::al */, $noreg, $noreg 175 %20:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg 176 %21:gprnopc = nuw nsw t2ADDrs %20, %19, 27, 14 /* CC::al */, $noreg, $noreg 177 %0:rgpr = COPY %21 178 %24:gprlr = t2DoLoopStart %0 179 %25:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg 180 %23:gpr = COPY %25 181 %1:gpr = COPY %24 182 %35:gprnopc = COPY %15 183 184 bb.2.vector.body: 185 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 186 187 %2:rgpr = PHI %13, %bb.1, %10, %bb.2 188 %3:rgpr = PHI %14, %bb.1, %9, %bb.2 189 %4:tgpreven = PHI %23, %bb.1, %8, %bb.2 190 %5:gprlr = PHI %1, %bb.1, %11, %bb.2 191 %6:rgpr = PHI %35, %bb.1, %7, %bb.2 192 %26:vccr = MVE_VCTP16 %6, 0, $noreg 193 %27:rgpr = t2SUBri %6, 8, 14 /* CC::al */, $noreg, $noreg 194 %7:gpr = COPY %27 195 %28:rgpr, %29:mqpr = MVE_VLDRHU16_post %2, 16, 1, %26 :: (load (s128) from %ir.lsr.iv35, align 2) 196 %30:rgpr, %31:mqpr = MVE_VLDRHU16_post %3, 16, 1, %26 :: (load (s128) from %ir.lsr.iv12, align 2) 197 %32:tgpreven = MVE_VMLADAVas16 %4, killed %31, killed %29, 1, %26 198 %8:gpr = COPY %32 199 %9:gpr = COPY %30 200 %10:gpr = COPY %28 201 %33:gprlr = t2LoopDec %5, 1 202 %11:gpr = COPY %33 203 t2LoopEnd %33, %bb.2, implicit-def dead $cpsr 204 t2B %bb.3, 14 /* CC::al */, $noreg 205 206 bb.3.for.cond.cleanup: 207 %12:gpr = PHI %16, %bb.4, %8, %bb.2 208 $r0 = COPY %12 209 tBX_RET 14 /* CC::al */, $noreg, implicit $r0 210 211... 212