| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 101 struct AMDGPUIncomingArgHandler : public AMDGPUValueHandler { struct
102 uint64_t StackUsed = 0;
104 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, in AMDGPUIncomingArgHandler() function
108 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
119 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
145 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, in assignValueToAddress()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() argument
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() function
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() function
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() function
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() argument
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler { struct
84 uint64_t StackUsed = 0;
86 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI) in AMDGPUIncomingArgHandler() argument
89 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
105 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
125 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, in assignValueToAddress()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 96 struct AMDGPUIncomingArgHandler : public AMDGPUValueHandler { struct
97 uint64_t StackUsed = 0;
99 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, in AMDGPUIncomingArgHandler() argument
103 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
114 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
140 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, in assignValueToAddress()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 96 struct AMDGPUIncomingArgHandler : public AMDGPUValueHandler { struct
97 uint64_t StackUsed = 0;
99 AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI, in AMDGPUIncomingArgHandler() argument
103 Register getStackAddress(uint64_t Size, int64_t Offset, in getStackAddress()
114 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
140 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize, in assignValueToAddress()
|