/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/x86/cpu/intel_common/ |
H A D | car.S | 22 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/x86/include/asm/ |
H A D | mtrr.h | 28 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/x86/include/asm/ |
H A D | mtrr.h | 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/ |
H A D | mtrr.h | 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/x86/include/asm/ |
H A D | mtrr.h | 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/x86/include/asm/ |
H A D | mtrr.h | 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/x86/include/asm/ |
H A D | mtrr.h | 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/x86/include/asm/ |
H A D | mtrr.h | 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) macro
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