1//
2// Copyright 2019 Ettus Research, A National Instruments Company
3//
4// SPDX-License-Identifier: LGPL-3.0-or-later
5//
6// Module: PkgChdrUtils
7//
8// Description: Various types, constants, and functions for interacting with
9// the RFNoC CHDR bus infrastructure.
10//
11
12
13
14package PkgChdrUtils;
15
16  import PkgChdrData::*;
17
18
19  //---------------------------------------------------------------------------
20  // Type Definitions
21  //---------------------------------------------------------------------------
22
23  //----------------------
24  // AXIS-CHDR Definitions
25  //----------------------
26
27  // Expose the CHDR word and item/sample data types and methods in the
28  // ChdrData class. The width of these types is a class parameter.
29  export PkgChdrData::ChdrData;
30
31  // CHDR header fields
32  typedef enum bit [2:0] {
33    CHDR_MANAGEMENT   = 3'd0,
34    CHDR_STRM_STATUS  = 3'd1,
35    CHDR_STRM_CMD     = 3'd2,
36    CHDR_RESERVED_0   = 3'd3,
37    CHDR_CONTROL      = 3'd4,
38    CHDR_RESERVED_1   = 3'd5,
39    CHDR_DATA_NO_TS   = 3'd6,
40    CHDR_DATA_WITH_TS = 3'd7
41  } chdr_pkt_type_t;                    // CHDR Packet Type
42
43  typedef bit [ 5:0] chdr_vc_t;         // CHDR Virtual Channel field
44  typedef bit [ 0:0] chdr_eob_t;        // CHDR End of Burst field
45  typedef bit [ 0:0] chdr_eov_t;        // CHDR End of Vector field
46  typedef bit [ 4:0] chdr_num_mdata_t;  // CHDR Num Metadata field
47  typedef bit [15:0] chdr_seq_num_t;    // CHDR SeqNum field
48  typedef bit [15:0] chdr_length_t;     // CHDR Length field
49  typedef bit [15:0] chdr_epid_t;       // CHDR EPID field
50  typedef bit [63:0] chdr_timestamp_t;  // CHDR Timestamp field
51
52  // CHDR Context Field Identifiers
53  typedef enum bit [3:0] {
54    CONTEXT_FIELD_HDR    = 4'd0,
55    CONTEXT_FIELD_HDR_TS = 4'd1,
56    CONTEXT_FIELD_TS     = 4'd2,
57    CONTEXT_FIELD_MDATA  = 4'd3
58  } chdr_context_type_t;
59
60  //----------------------
61  // AXIS-Ctrl Definitions
62  //----------------------
63
64  // The fundamental unit of the AXIS-Ctrl (control) bus, which is always 32 bits
65  typedef logic [31:0] ctrl_word_t;
66
67  typedef enum bit [3:0] {
68    CTRL_OP_SLEEP      = 4'd0,
69    CTRL_OP_WRITE      = 4'd1,
70    CTRL_OP_READ       = 4'd2,
71    CTRL_OP_WRITE_READ = 4'd3,
72    CTRL_OP_RESERVED_0 = 4'd4,
73    CTRL_OP_RESERVED_1 = 4'd5,
74    CTRL_OP_RESERVED_2 = 4'd6,
75    CTRL_OP_RESERVED_3 = 4'd7,
76    CTRL_OP_RESERVED_4 = 4'd8,
77    CTRL_OP_RESERVED_5 = 4'd9
78  } ctrl_opcode_t;                    // Control OpCode Type
79
80  typedef enum bit [1:0] {
81    CTRL_STS_OKAY    = 2'd0,
82    CTRL_STS_CMDERR  = 2'd1,
83    CTRL_STS_TSERR   = 2'd2,
84    CTRL_STS_WARNING = 2'd3
85  } ctrl_status_t;                    // Control OpCode Type
86
87  typedef bit  [5:0] ctrl_seq_num_t;  // AXIS-Ctrl SeqNum field
88  typedef bit  [3:0] ctrl_num_data_t; // AXIS-Ctrl NumData field
89  typedef bit  [9:0] ctrl_port_t;     // AXIS-Ctrl source/destination port field
90  typedef bit  [3:0] ctrl_byte_en_t;  // AXIS-Ctrl ByteEnable field
91  typedef bit [19:0] ctrl_address_t;  // AXIS-Ctrl Address field
92
93  //-------------------------------
94  // CHDR Type-Specific Definitions
95  //-------------------------------
96
97  // CHDR Status packet fields
98  typedef enum bit [3:0] {
99    STRS_OKAY    = 4'd0,
100    STRS_CMDERR  = 4'd1,
101    STRS_SEQERR  = 4'd2,
102    STRS_DATAERR = 4'd3,
103    STRS_RTERR   = 4'd4
104  } chdr_strs_status_t;  // CHDR stream status packet status field
105
106  // CHDR Control packet fields
107  typedef enum bit [3:0] {
108    STRC_INIT    = 4'd0,
109    STRC_PING    = 4'd1,
110    STRC_RESYNC  = 4'd2
111  } chdr_strc_opcode_t;  // CHDR stream command packet opcode filed
112
113  // CHDR Management packet field
114  typedef enum bit [2:0] {
115    CHDR_W_64      = 3'd0,
116    CHDR_W_128     = 3'd1,
117    CHDR_W_256     = 3'd2,
118    CHDR_W_512     = 3'd3,
119    CHDR_W_INVALID = 3'd7
120  } chdr_mgmt_width_t;   // CHDR management packet CHDR Width field
121
122  function automatic chdr_mgmt_width_t translate_chdr_w(int bitwidth);
123    case (bitwidth)
124      64:      return CHDR_W_64;
125      128:     return CHDR_W_128;
126      256:     return CHDR_W_256;
127      512:     return CHDR_W_512;
128      default: return CHDR_W_INVALID;
129    endcase
130  endfunction : translate_chdr_w
131
132  typedef enum bit [7:0] {
133    MGMT_OP_NOP         = 8'd0,
134    MGMT_OP_ADVERTISE   = 8'd1,
135    MGMT_OP_SEL_DEST    = 8'd2,
136    MGMT_OP_RETURN      = 8'd3,
137    MGMT_OP_INFO_REQ    = 8'd4,
138    MGMT_OP_INFO_RESP   = 8'd5,
139    MGMT_OP_CFG_WR_REQ  = 8'd6,
140    MGMT_OP_CFG_RD_REQ  = 8'd7,
141    MGMT_OP_CFG_RD_RESP = 8'd8
142  } chdr_mgmt_opcode_t;  // CHDR management packet OpCode field
143
144
145  //---------------------------------------------------------------------------
146  // Packet Data Structures
147  //---------------------------------------------------------------------------
148
149  // CHDR packet header
150  typedef struct packed {
151    chdr_vc_t        vc;
152    chdr_eob_t       eob;
153    chdr_eov_t       eov;
154    chdr_pkt_type_t  pkt_type;
155    chdr_num_mdata_t num_mdata;
156    chdr_seq_num_t   seq_num;
157    chdr_length_t    length;
158    chdr_epid_t      dst_epid;
159  } chdr_header_t;
160
161  // AXIS-Ctrl packet header
162  typedef struct packed {
163    // Word 1
164    bit [ 5:0]      _rsvd_0;
165    ctrl_port_t     rem_dst_port;
166    chdr_epid_t     rem_dst_epid;
167    // Word 0
168    bit             is_ack;
169    bit             has_time;
170    ctrl_seq_num_t  seq_num;
171    ctrl_num_data_t num_data;
172    ctrl_port_t     src_port;
173    ctrl_port_t     dst_port;
174  } axis_ctrl_header_t;
175
176  // AXIS-Ctrl packet header
177  typedef struct packed {
178    ctrl_status_t status;
179    bit [ 1:0]    _rsvd_0;
180    ctrl_opcode_t op_code;
181    bit [ 3:0]    byte_enable;
182    bit [19:0]    address;
183  } ctrl_op_word_t;
184
185  // Ctrl packet header when in the payload of a CHDR packet
186  typedef struct packed {
187    bit [15:0]      _rsvd_0;
188    chdr_epid_t     src_epid;
189    bit             is_ack;
190    bit             has_time;
191    ctrl_seq_num_t  seq_num;
192    ctrl_num_data_t num_data;
193    ctrl_port_t     src_port;
194    ctrl_port_t     dst_port;
195  } chdr_ctrl_header_t;
196
197  // CHDR stream status packet payload
198  typedef struct packed {
199    // Word 3
200    bit [47:0]          status_info;
201    bit [15:0]          buff_info;
202    // Word 2
203    bit [63:0]          xfer_count_bytes;
204    // Word 1
205    bit [39:0]          xfer_count_pkts;
206    bit [23:0]          capacity_pkts;
207    // Word 0
208    bit [39:0]          capacity_bytes;
209    bit [ 3:0]          _rsvd_0;
210    chdr_strs_status_t  status;
211    chdr_epid_t         src_epid;
212  } chdr_str_status_t;
213
214  // CHDR stream command packet payload
215  typedef struct packed {
216    // Word 1
217    bit [63:0]          num_bytes;
218    // Word 0
219    bit [39:0]          num_pkts;
220    bit [ 3:0]          op_data;
221    chdr_strc_opcode_t  op_code;
222    chdr_epid_t         src_epid;
223  } chdr_str_command_t;
224
225  // CHDR management packet header
226  typedef struct packed {
227    bit [15:0]          prot_ver;
228    chdr_mgmt_width_t   chdr_width;
229    bit [18:0]          _rsvd_0;
230    bit [ 9:0]          num_hops;
231    chdr_epid_t         src_epid;
232  } chdr_mgmt_header_t;
233
234  // CHDR management packet operation
235  typedef struct packed {
236    bit [47:0]          op_payload;
237    chdr_mgmt_opcode_t  op_code;
238    bit [ 7:0]          ops_pending;
239  } chdr_mgmt_op_t;
240
241  // CHDR management packet
242  typedef struct {
243    chdr_mgmt_header_t  header;
244    chdr_mgmt_op_t      ops[$];
245  } chdr_mgmt_t;
246
247
248endpackage : PkgChdrUtils
249