1//
2// Copyright 2011 Ettus Research LLC
3//
4// This program is free software: you can redistribute it and/or modify
5// it under the terms of the GNU General Public License as published by
6// the Free Software Foundation, either version 3 of the License, or
7// (at your option) any later version.
8//
9// This program is distributed in the hope that it will be useful,
10// but WITHOUT ANY WARRANTY; without even the implied warranty of
11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12// GNU General Public License for more details.
13//
14// You should have received a copy of the GNU General Public License
15// along with this program.  If not, see <http://www.gnu.org/licenses/>.
16//
17
18module fifo_tb();
19
20   reg clk = 0;
21   reg rst = 1;
22   reg clear = 0;
23   initial #1000 rst = 0;
24   always #50 clk = ~clk;
25
26   reg [18:0] f19a;
27   wire [18:0] f19b, f19c, f19d;
28   wire [35:0] f36a, f36b;
29
30   reg 	       f19a_sr = 0;
31   wire        f19b_sr, f19c_sr, f19d_sr, f36a_sr, f36b_sr;
32   wire        f19a_dr, f19b_dr, f19c_dr, f19d_dr, f36a_dr, f36b_dr;
33
34   fifo_short #(.WIDTH(19)) fifo_short1
35     (.clk(clk),.reset(rst),.clear(clear),
36      .datain(f19a),.src_rdy_i(f19a_sr),.dst_rdy_o(f19a_dr),
37      .dataout(f19b),.src_rdy_o(f19b_sr),.dst_rdy_i(f19b_dr) );
38
39   fifo19_to_fifo36 fifo19_to_fifo36
40     (.clk(clk),.reset(rst),.clear(clear),
41      .f19_datain(f19b),.f19_src_rdy_i(f19b_sr),.f19_dst_rdy_o(f19b_dr),
42      .f36_dataout(f36a),.f36_src_rdy_o(f36a_sr),.f36_dst_rdy_i(f36a_dr) );
43
44   fifo_short #(.WIDTH(36)) fifo_short2
45     (.clk(clk),.reset(rst),.clear(clear),
46      .datain(f36a),.src_rdy_i(f36a_sr),.dst_rdy_o(f36a_dr),
47      .dataout(f36b),.src_rdy_o(f36b_sr),.dst_rdy_i(f36b_dr) );
48
49   fifo36_to_fifo19 fifo36_to_fifo19
50     (.clk(clk),.reset(rst),.clear(clear),
51      .f36_datain(f36b),.f36_src_rdy_i(f36b_sr),.f36_dst_rdy_o(f36b_dr),
52      .f19_dataout(f19c),.f19_src_rdy_o(f19c_sr),.f19_dst_rdy_i(f19c_dr) );
53
54   fifo_short #(.WIDTH(19)) fifo_short3
55     (.clk(clk),.reset(rst),.clear(clear),
56      .datain(f19c),.src_rdy_i(f19c_sr),.dst_rdy_o(f19c_dr),
57      .dataout(f19d),.src_rdy_o(f19d_sr),.dst_rdy_i(f19d_dr) );
58
59   assign f19d_dr = 1;
60
61    always @(posedge clk)
62     if(f19a_sr & f19a_dr)
63       $display("18IN: %h", f19a);
64
65    always @(posedge clk)
66     if(f19d_sr & f19d_dr)
67       $display("                            18OUT: %h", f19d);
68
69   always @(posedge clk)
70     if(f36b_sr & f36b_dr)
71       $display("             36: %h", f36b);
72
73   initial $dumpfile("fifo_tb.vcd");
74   initial $dumpvars(0,fifo_tb);
75
76   initial
77     begin
78	@(negedge rst);
79	@(posedge clk);
80	repeat (2)
81	  begin
82	     f19a <= 19'h1_AA01;
83	     f19a_sr <= 1;
84	     @(posedge clk);
85	     f19a <= 19'h0_AA02;
86	     repeat (4)
87	       begin
88		  @(posedge clk);
89		  f19a <= f19a + 1;
90	       end
91	     f19a[18:16] <= 3'b010;
92	     @(posedge clk);
93	     f19a_sr <= 0;
94	     f19a <= 19'h7_FFFF;
95	     @(posedge clk);
96	  end
97	#20000 $finish;
98     end
99endmodule // longfifo_tb
100