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Searched defs:wrusedw (Results 1 – 17 of 17) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/
H A Dfifo_4kx16_dc.v59 output [11:0] wrusedw; port
67 wire [11:0] wrusedw = sub_wire1[11:0]; net
H A Dfifo_4k_18.v62 output [11:0] wrusedw; port
70 wire [11:0] wrusedw = sub_wire1[11:0]; net
H A Dfifo_2k_bb.v54 output [10:0] wrusedw; port
H A Dfifo_4k_bb.v54 output [11:0] wrusedw; port
H A Dfifo_4kx16_dc_bb.v54 output [11:0] wrusedw; port
H A Dfifo_2k.v3037 output [10:0] wrusedw; port
3242 output [10:0] wrusedw; port
3250 wire [10:0] wrusedw = sub_wire1[10:0]; net
H A Dfifo_4k.v3189 output [11:0] wrusedw; port
3394 output [11:0] wrusedw; port
3402 wire [11:0] wrusedw = sub_wire1[11:0]; net
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/models/
H A Dfifo_1c_2k.v22 output [10:0] wrusedw; port
35 reg [10:0] wrusedw; register
H A Dfifo_1c_4k.v22 output [7:0] wrusedw; port
35 reg [7:0] wrusedw; register
H A Dfifo_1c_1k.v22 output [9:0] wrusedw; port
35 reg [9:0] wrusedw; register
H A Dfifo_1k.v16 output [9:0] wrusedw port
H A Dfifo_2k.v16 output [10:0] wrusedw port
H A Dfifo_4k.v16 output [11:0] wrusedw port
H A Dfifo_4k_18.v9 output [11:0] wrusedw, port
H A Dfifo.v24 output reg [addr_bits-1:0] wrusedw; port
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/inband_lib/
H A Drx_buffer_inband.v63 wire [11:0] wrusedw; net
/dports/cad/verilator/verilator-4.216/test_regress/t/
H A Dt_altera_lpm.v6098 output [lpm_widthu-1:0] wrusedw; port
6538 output [lpm_widthu-1:0] wrusedw; port