1 2 3module fifo_4k 4 ( input [15:0] data, 5 input wrreq, 6 input rdreq, 7 input rdclk, 8 input wrclk, 9 input aclr, 10 output [15:0] q, 11 output rdfull, 12 output rdempty, 13 output [11:0] rdusedw, 14 output wrfull, 15 output wrempty, 16 output [11:0] wrusedw 17 ); 18 19fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 20 ( data, wrreq, rdreq, rdclk, wrclk, aclr, q, 21 rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); 22 23endmodule // fifo_1k 24 25