| /dports/devel/llvm90/llvm-9.0.1.src/include/llvm/IR/ |
| H A D | Instruction.h | 161 return Opcode >= Shl && Opcode <= AShr;
171 return getOpcode() == AShr;
|
| /dports/devel/llvm80/llvm-8.0.1.src/include/llvm/IR/ |
| H A D | Instruction.h | 159 return Opcode >= Shl && Opcode <= AShr;
169 return getOpcode() == AShr;
|
| H A D | Operator.h | 143 OpC == Instruction::AShr || in isPossiblyExactOpcode()
426 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|
| /dports/security/klee/klee-2.2/lib/Module/ |
| H A D | Checks.cpp | 105 opcode != Instruction::AShr) in runOnModule()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 65 case Instruction::AShr: in getIntImmCostInst()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 65 case Instruction::AShr: in getIntImmCostInst()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 65 case Instruction::AShr: in getIntImmCostInst()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 72 case Instruction::AShr: in getIntImmCostInst()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 65 case Instruction::AShr: in getIntImmCostInst()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AVR/ |
| H A D | AVRShiftExpand.cpp | 124 case Instruction::AShr: in expand()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 65 case Instruction::AShr: in GetCpuSku()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 196 return Opcode >= Shl && Opcode <= AShr;
206 return getOpcode() == AShr;
|
| H A D | Operator.h | 143 OpC == Instruction::AShr || in isPossiblyExactOpcode()
446 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineNegator.cpp | 170 case Instruction::AShr: in visitImpl()
175 Value *BO = I->getOpcode() == Instruction::AShr in visitImpl()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Transforms/InstCombine/ |
| H A D | InstCombineNegator.cpp | 170 case Instruction::AShr: in visitImpl()
175 Value *BO = I->getOpcode() == Instruction::AShr in visitImpl()
|
| /dports/devel/llvm70/llvm-7.0.1.src/include/llvm/IR/ |
| H A D | Operator.h | 143 OpC == Instruction::AShr || in isPossiblyExactOpcode()
419 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 158 case Instruction::AShr:
378 Opcode == Instruction::AShr || UDivPow2) { in ginPlaceToPage()
435 if (Opcode == Instruction::LShr || Opcode == Instruction::AShr) in ginPlaceToPage()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 201 return Opcode >= Shl && Opcode <= AShr;
211 return getOpcode() == AShr;
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 196 return Opcode >= Shl && Opcode <= AShr;
206 return getOpcode() == AShr;
|
| H A D | Operator.h | 143 OpC == Instruction::AShr || in isPossiblyExactOpcode()
446 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|