Home
last modified time | relevance | path

Searched refs:MFVSR (Results 26 – 50 of 72) sorted by relevance

123

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
H A DPPCGenFastISel.inc1528 // FastEmit functions for PPCISD::MFVSR.
1727 case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0, Op0IsKill);
H A DPPCGenDAGISel.inc34925 /* 89825*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
39695 /* 99900*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
39708 /* 99923*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
39722 /* 99947*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
39775 /*100081*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
39910 /*100416*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
40122 /*100924*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
40155 /*100993*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
40596 /*101744*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
40605 /*101760*/ OPC_CheckOpcode, TARGET_VAL(PPCISD::MFVSR),
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1454 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8209 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13622 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13640 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13977 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
H A DPPCInstrVSX.td128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1531 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7667 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13181 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13199 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13536 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
H A DPPCInstrVSX.td128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1531 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
7667 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13181 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13199 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
13536 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
H A DPPCInstrVSX.td128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1634 case PPCISD::MFVSR: return "PPCISD::MFVSR";
8083 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv);
13664 assert(FirstInput.getOpcode() == PPCISD::MFVSR &&
13682 if (NextOp.getOpcode() != PPCISD::MFVSR)
14019 if (FirstInput.getOpcode() == PPCISD::MFVSR) {
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1634 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8083 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13664 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13682 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14019 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1634 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8083 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13664 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13682 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14019 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1639 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8077 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13788 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13806 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14143 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1634 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8083 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13664 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13682 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14019 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1634 case PPCISD::MFVSR: return "PPCISD::MFVSR"; in getTargetNodeName()
8083 SDValue Mov = DAG.getNode(PPCISD::MFVSR, dl, Op.getValueType(), Conv); in LowerFP_TO_INTDirectMove()
13664 assert(FirstInput.getOpcode() == PPCISD::MFVSR && in combineElementTruncationToVectorTruncation()
13682 if (NextOp.getOpcode() != PPCISD::MFVSR) in combineElementTruncationToVectorTruncation()
14019 if (FirstInput.getOpcode() == PPCISD::MFVSR) { in DAGCombineBuildVector()
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCInstrVSX.td76 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCInstrVSX.td76 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCInstrVSX.td76 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/
H A DPPCInstrVSX.td80 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/
H A DPPCInstrVSX.td76 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td101 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/
H A DPPCInstrVSX.td101 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td101 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/
H A DPPCInstrVSX.td88 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/
H A DPPCInstrVSX.td128 def PPCmfvsr : SDNode<"PPCISD::MFVSR", SDTUnaryOp, []>;

123