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Searched refs:PAD_CTL_PE (Results 51 – 75 of 679) sorted by relevance

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/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-rock64/u-boot-2021.07/board/phytec/phycore_imx8mp/
H A Dspl.c36 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
80 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-chip/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/toradex/verdin-imx8mm/
H A Dspl.c78 #define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
79 #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)

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