Home
last modified time | relevance | path

Searched refs:SHARE (Results 151 – 175 of 6596) sorted by relevance

12345678910>>...264

/dports/databases/postgresql96-client/postgresql-9.6.24/src/test/regress/sql/
H A Dlock.sql16 LOCK TABLE lock_tbl1 IN ACCESS SHARE MODE;
17 LOCK lock_tbl1 IN ROW SHARE MODE;
19 LOCK TABLE lock_tbl1 IN SHARE UPDATE EXCLUSIVE MODE;
20 LOCK TABLE lock_tbl1 IN SHARE MODE;
21 LOCK lock_tbl1 IN SHARE ROW EXCLUSIVE MODE;
28 LOCK TABLE lock_tbl1 IN ACCESS SHARE MODE NOWAIT;
29 LOCK TABLE lock_tbl1 IN ROW SHARE MODE NOWAIT;
31 LOCK TABLE lock_tbl1 IN SHARE UPDATE EXCLUSIVE MODE NOWAIT;
32 LOCK TABLE lock_tbl1 IN SHARE MODE NOWAIT;
33 LOCK TABLE lock_tbl1 IN SHARE ROW EXCLUSIVE MODE NOWAIT;
/dports/net/samba412/samba-4.12.15/source3/script/tests/
H A Dtest_inherit_owner.sh9 Usage: $0 SERVER USERNAME PASSWORD PREFIX SMBCLIENT SMBCACLS NET SHARE INH_WIN INH_UNIX <additional…
21 SHARE="$8"
146 testit "$TEST_LABEL - create subdir under root" create_dir $SHARE tmp.$$/subdir
147 testit "$TEST_LABEL - verify subdir win owner" win_owner_is $SHARE tmp.$$/subdir "$WIN_OWNER_AFTER_…
149 testit "$TEST_LABEL - create file under root" create_file $SHARE tmp.$$/afile
150 testit "$TEST_LABEL - verify file win owner" win_owner_is $SHARE tmp.$$/afile "$WIN_OWNER_AFTER_CRE…
152 testit "$TEST_LABEL - change dir owner" set_win_owner $SHARE tmp.$$/subdir "$SERVER\smbget_user"
155 testit "$TEST_LABEL - change file owner" set_win_owner $SHARE tmp.$$/afile "$SERVER\smbget_user"
158 testit "$TEST_LABEL - cleanup subdir" cleanup_dir $SHARE tmp.$$/subdir
159 testit "$TEST_LABEL - cleanup file" cleanup_file $SHARE tmp.$$/afile
[all …]
/dports/databases/xtrabackup8/percona-xtrabackup-8.0.14/mysql-test/r/
H A Dlocking_with_out_key.result38 # SHARE ...
39 SELECT * FROM t1 FOR SHARE;
41 SELECT * FROM t1 FOR SHARE NOWAIT;
43 SELECT * FROM t1 FOR SHARE SKIP LOCKED;
49 SELECT * FROM t1, t2 FOR SHARE OF t1 FOR SHARE OF t2;
55 SELECT * FROM t1, t2 FOR SHARE OF t1 NOWAIT FOR SHARE OF t2 NOWAIT;
97 # SHARE ...
98 SELECT * FROM t1 FOR SHARE;
100 SELECT * FROM t1 FOR SHARE NOWAIT;
110 SELECT * FROM t1, t2 FOR SHARE OF t1 FOR SHARE OF t2;
[all …]
/dports/x11/xscreensaver/xscreensaver-5.44/hacks/
H A Dvms_axp.opt2 SYS$SHARE:DECW$XMULIBSHR.EXE/SHARE
3 SYS$SHARE:DECW$XTSHR.EXE/SHARE
4 SYS$SHARE:DECW$XLIBSHR.EXE/SHARE
H A Dvms_decc.opt2 SYS$SHARE:DECW$XMULIBSHR.EXE/SHARE
3 SYS$SHARE:DECW$XTSHR.EXE/SHARE
4 SYS$SHARE:DECW$XLIBSHR.EXE/SHARE
H A Dvms_decc_12.opt2 SYS$SHARE:DECW$XMULIBSHRR5.EXE/SHARE
3 SYS$SHARE:DECW$XTLIBSHRR5.EXE/SHARE
4 SYS$SHARE:DECW$XLIBSHR.EXE/SHARE
H A Dvms_axp_12.opt2 SYS$SHARE:DECW$XMULIBSHRR5.EXE/SHARE
3 SYS$SHARE:DECW$XTLIBSHRR5.EXE/SHARE
4 SYS$SHARE:DECW$XLIBSHR.EXE/SHARE
/dports/graphics/pgplot/pgplot/sys_vms/
H A Dmake_pgmdemo.com39 $ XMOTIF12 = F$SEARCH("SYS$SHARE:DECW$XMLIBSHR12.EXE")
40 $ XMOTIF11 = F$SEARCH("SYS$SHARE:DECW$XMLIBSHR.EXE")
49 SYS$SHARE:DECW$XMLIBSHR12.EXE/share
50 SYS$SHARE:DECW$XTLIBSHRR5.EXE/share
51 SYS$SHARE:DECW$XLIBSHR.EXE/share
52 SYS$SHARE:DECC$SHR.EXE/share
61 SYS$SHARE:DECW$XMLIBSHR.EXE/share
62 SYS$SHARE:DECW$XTSHR.EXE/share
63 SYS$SHARE:DECW$XLIBSHR.EXE/share
64 SYS$SHARE:DECC$SHR.EXE/share
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir28 # SHARE: stack:
29 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
30 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
35 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
36 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
37 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: 1, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/net/samba412/samba-4.12.15/source4/client/tests/
H A Dtest_cifsdd.sh22 SHARE=tmp
55 if=$sourcepath of=//$SERVER/$SHARE/$sourcepath bs=$bs
57 if=//$SERVER/$SHARE/$sourcepath of=$destpath bs=$bs
62 if=//$SERVER/$SHARE/$sourcepath of=//$SERVER/$SHARE/$sourcepath bs=$bs
64 if=//$SERVER/$SHARE/$sourcepath of=//$SERVER/$SHARE/$destpath bs=$bs
66 if=//$SERVER/$SHARE/$destpath of=$destpath bs=$bs
/dports/net-mgmt/wmi-client/wmi-1.3.16/Samba/source/script/tests/
H A Dtest_cifsdd.sh19 SHARE=tmp
61 if=$sourcepath of=//$SERVER/$SHARE/$sourcepath bs=$bs || failtest
63 if=//$SERVER/$SHARE/$sourcepath of=$destpath bs=$bs || failtest
68 if=//$SERVER/$SHARE/$sourcepath of=//$SERVER/$SHARE/$sourcepath bs=$bs || failtest
70 if=//$SERVER/$SHARE/$sourcepath of=//$SERVER/$SHARE/$destpath bs=$bs || failtest
72 if=//$SERVER/$SHARE/$destpath of=$destpath bs=$bs || failtest
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-spill-wrong-stack-id.mir25 # SHARE: stack:
26 # SHARE: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
27 # SHARE: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
28 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
29 # SHARE: - { id: 1, name: '', type: spill-slot, offset: 0, size: 8, alignment: 4,
30 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
31 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
32 # SHARE: - { id: 2, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
33 # SHARE: stack-id: sgpr-spill, callee-saved-register: '', callee-saved-restored: true,
34 # SHARE: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
[all …]

12345678910>>...264