/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMScheduleA57.td | 75 // LDM, base reg in list 167 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 383 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 447 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 495 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 615 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 652 // 1(1) "S, I0/I1" for imm or reg plus 684 // 1(1) "S, I0/I1" both for reg or imm 796 // VMOV: 3cyc "F0/F1" for imm/reg 808 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 74 // LDM, base reg in list 169 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 385 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 449 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 497 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 617 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 654 // 1(1) "S, I0/I1" for imm or reg plus 686 // 1(1) "S, I0/I1" both for reg or imm 798 // VMOV: 3cyc "F0/F1" for imm/reg 810 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 74 // LDM, base reg in list 169 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 385 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 449 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 497 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 617 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 654 // 1(1) "S, I0/I1" for imm or reg plus 686 // 1(1) "S, I0/I1" both for reg or imm 798 // VMOV: 3cyc "F0/F1" for imm/reg 810 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/ARM/ |
H A D | ARMScheduleA57.td | 75 // LDM, base reg in list 167 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 383 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 447 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 495 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 615 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 652 // 1(1) "S, I0/I1" for imm or reg plus 684 // 1(1) "S, I0/I1" both for reg or imm 796 // VMOV: 3cyc "F0/F1" for imm/reg 808 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 74 // LDM, base reg in list 169 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 385 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 449 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 497 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 617 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 654 // 1(1) "S, I0/I1" for imm or reg plus 686 // 1(1) "S, I0/I1" both for reg or imm 798 // VMOV: 3cyc "F0/F1" for imm/reg 810 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 74 // LDM, base reg in list 169 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 385 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 449 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 497 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 617 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 654 // 1(1) "S, I0/I1" for imm or reg plus 686 // 1(1) "S, I0/I1" both for reg or imm 798 // VMOV: 3cyc "F0/F1" for imm/reg 810 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 75 // LDM, base reg in list 167 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 383 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 447 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 495 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 615 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 652 // 1(1) "S, I0/I1" for imm or reg plus 684 // 1(1) "S, I0/I1" both for reg or imm 796 // VMOV: 3cyc "F0/F1" for imm/reg 808 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 75 // LDM, base reg in list 167 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 383 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 447 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 495 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 615 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 652 // 1(1) "S, I0/I1" for imm or reg plus 684 // 1(1) "S, I0/I1" both for reg or imm 796 // VMOV: 3cyc "F0/F1" for imm/reg 808 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2792 let OpType = "reg"; 2801 let OpType = "reg"; 2971 let OpType = "reg"; 3157 let OpType = "reg"; 3168 let OpType = "reg"; 3179 let OpType = "reg"; [all …]
|
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2743 let OpType = "reg"; 2752 let OpType = "reg"; 2922 let OpType = "reg"; 3108 let OpType = "reg"; 3119 let OpType = "reg"; 3130 let OpType = "reg"; [all …]
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2797 let OpType = "reg"; 2806 let OpType = "reg"; 2976 let OpType = "reg"; 3162 let OpType = "reg"; 3173 let OpType = "reg"; 3184 let OpType = "reg"; [all …]
|
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2743 let OpType = "reg"; 2752 let OpType = "reg"; 2922 let OpType = "reg"; 3108 let OpType = "reg"; 3119 let OpType = "reg"; 3130 let OpType = "reg"; [all …]
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2797 let OpType = "reg"; 2806 let OpType = "reg"; 2976 let OpType = "reg"; 3162 let OpType = "reg"; 3173 let OpType = "reg"; 3184 let OpType = "reg"; [all …]
|
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 177 // check reg 0 for ARM_AM::PC 378 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 442 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 490 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 614 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 651 // 1(1) "S, I0/I1" for imm or reg plus 683 // 1(1) "S, I0/I1" both for reg or imm 795 // VMOV: 3cyc "F0/F1" for imm/reg 807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
H A D | ARMScheduleA57.td | 157 // B, BX, BL, BLX (imm, reg != LR, reg == LR), CBZ, CBNZ 377 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate 441 // LDRD pre-indexed: 5(2) cyc for reg, 4(1) cyc for imm. 489 // LDRD post-indexed: 4(2) cyc for reg, 4(1) cyc for imm. 613 // STRH,STRD: 3cyc "I0/I1, S" for minus reg, 1cyc S for imm or for plus reg. 631 // 1(1) "S, I0/I1" for plus reg 650 // 1(1) "S, I0/I1" for imm or reg plus 682 // 1(1) "S, I0/I1" both for reg or imm 794 // VMOV: 3cyc "F0/F1" for imm/reg 806 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg [all …]
|
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2743 let OpType = "reg"; 2752 let OpType = "reg"; 3102 let OpType = "reg"; 3113 let OpType = "reg"; 3124 let OpType = "reg"; 3135 let OpType = "reg"; [all …]
|
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2743 let OpType = "reg"; 2752 let OpType = "reg"; 3102 let OpType = "reg"; 3113 let OpType = "reg"; 3124 let OpType = "reg"; 3135 let OpType = "reg"; [all …]
|
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrFormats.td | 36 // "reg" for <INSN>R and "mem" for <INSN>. 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 144 let KeyCol = ["reg"]; 2743 let OpType = "reg"; 2752 let OpType = "reg"; 3102 let OpType = "reg"; 3113 let OpType = "reg"; 3124 let OpType = "reg"; 3135 let OpType = "reg"; [all …]
|