/netbsd/external/gpl3/gdb/dist/include/opcode/ |
H A D | arc.h | 82 STORE, enumerator
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/netbsd/external/gpl3/binutils.old/dist/include/opcode/ |
H A D | arc.h | 82 STORE, enumerator
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/netbsd/external/gpl3/binutils/dist/include/opcode/ |
H A D | arc.h | 82 STORE, enumerator
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/netbsd/external/gpl3/gdb.old/dist/include/opcode/ |
H A D | arc.h | 82 STORE, enumerator
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/netbsd/crypto/external/bsd/openssl/dist/crypto/ |
H A D | trace.c | 137 TRACE_CATEGORY_(STORE),
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 893 case ISD::STORE: return SelectStore(N); in Select() 972 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) { in isMemOPCandidate() 1036 if (I->getOpcode() != ISD::STORE) in ppAddrReorderAddShl() 1101 if (Opc != ISD::LOAD && Opc != ISD::STORE) in ppAddrRewriteAndSrl() 2252 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE) in rebalanceAddressTrees()
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H A D | HexagonISelLoweringHVX.cpp | 168 setOperationAction(ISD::STORE, T, Custom); in initializeHVXLowering() 255 setOperationAction(ISD::STORE, VecTy, Custom); in initializeHVXLowering() 1835 if (MemOpc == ISD::STORE) { in SplitHvxMemOp() 2067 case ISD::STORE: in LowerHvxOperation() 2159 case ISD::STORE: { in LowerHvxOperationWrapper()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 73 setOperationAction(ISD::STORE, MVT::i8, Custom); in R600TargetLowering() 74 setOperationAction(ISD::STORE, MVT::i32, Custom); in R600TargetLowering() 75 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in R600TargetLowering() 76 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in R600TargetLowering() 462 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
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H A D | SIISelLowering.cpp | 152 setOperationAction(ISD::STORE, MVT::v2i32, Custom); in SITargetLowering() 153 setOperationAction(ISD::STORE, MVT::v3i32, Custom); in SITargetLowering() 154 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in SITargetLowering() 155 setOperationAction(ISD::STORE, MVT::v5i32, Custom); in SITargetLowering() 158 setOperationAction(ISD::STORE, MVT::i1, Custom); in SITargetLowering() 252 case ISD::STORE: in SITargetLowering() 575 case ISD::STORE: in SITargetLowering() 828 setTargetDAGCombine(ISD::STORE); in SITargetLowering() 1587 case ISD::STORE: in isTypeDesirableForOp() 4494 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation() [all …]
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/netbsd/external/gpl3/binutils.old/dist/cpu/ |
H A D | frv.opc | 303 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 338 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 370 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 402 /* STORE */ UNIT_I01, /* store in I0 or I1 unit. */
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/netbsd/external/gpl3/gdb.old/dist/cpu/ |
H A D | frv.opc | 303 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 338 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 370 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 402 /* STORE */ UNIT_I01, /* store in I0 or I1 unit. */
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/netbsd/external/gpl3/gdb/dist/cpu/ |
H A D | frv.opc | 303 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 338 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 370 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 402 /* STORE */ UNIT_I01, /* store in I0 or I1 unit. */
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/netbsd/external/gpl3/binutils/dist/cpu/ |
H A D | frv.opc | 303 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 338 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 370 /* STORE */ UNIT_I0, /* store only in I0 unit. */ 402 /* STORE */ UNIT_I01, /* store in I0 or I1 unit. */
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.td | 395 // STORE instructions 396 class STORE<BPFWidthModifer SizeOp, string OpcodeStr, list<dag> Pattern> 412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
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/netbsd/sys/arch/m68k/fpsp/ |
H A D | satan.sa | 302 *-- -ATAN(|F|), WE NEED TO STORE ONLY ATAN(|F|). 318 *--CREATE ATAN(F) AND STORE IT IN ATANF, AND
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 134 setOperationAction(ISD::STORE, MVT::i32, Custom); in XCoreTargetLowering() 170 setTargetDAGCombine(ISD::STORE); in XCoreTargetLowering() 207 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation() 1779 case ISD::STORE: { in PerformDAGCombine()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 98 setOperationAction(ISD::STORE, VecTys[i], Legal); in MipsSETargetLowering() 209 setOperationAction(ISD::STORE, MVT::i32, Custom); in MipsSETargetLowering() 224 setOperationAction(ISD::STORE, MVT::f64, Custom); in MipsSETargetLowering() 327 setOperationAction(ISD::STORE, Ty, Legal); in addMSAIntType() 380 setOperationAction(ISD::STORE, Ty, Legal); in addMSAFloatType() 453 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
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/netbsd/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kISelDAGToDAG.cpp | 755 Parent->getOpcode() != ISD::STORE))) { in SelectARII()
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/netbsd/crypto/external/bsd/openssl/dist/doc/man3/ |
H A D | OSSL_trace_set_channel.pod | 190 Traces STORE operations.
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/netbsd/external/gpl3/gdb/dist/sim/bfin/ |
H A D | ChangeLog | 690 * bfin-sim.c (decode_dsp32shift_0): Use STORE() for VIT_MAX insns. 940 * bfin-sim.c (decode_dsp32alu_0): Call STORE instead of SET_DREG for 943 (decode_dsp32shift_0): Call STORE instead of SET_DREG for PACK,
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/netbsd/external/gpl3/gdb.old/dist/sim/bfin/ |
H A D | ChangeLog | 690 * bfin-sim.c (decode_dsp32shift_0): Use STORE() for VIT_MAX insns. 940 * bfin-sim.c (decode_dsp32alu_0): Call STORE instead of SET_DREG for 943 (decode_dsp32shift_0): Call STORE instead of SET_DREG for PACK,
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/netbsd/crypto/external/bsd/openssl/dist/doc/man1/ |
H A D | openssl.pod | 740 =item B<STORE> 742 Traces STORE operations.
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/netbsd/external/gpl3/gdb/dist/opcodes/ |
H A D | arc-tbl.h | 16501 { "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { RC, BRAKET, L… 16504 { "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC, BRAKET,… 16507 { "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET,… 16531 { "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, BRAKETdup }, {… 16534 { "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, BRAKETdup }, { … 16537 { "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, SIMM9_8, BRAKE… 16540 { "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, SIMM9_8, BRAKET… 16543 { "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, LIMM, BRAKETdup },… 16546 { "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, LIMM, BRAKETdup }, … 16549 { "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, LL64, { LIMM, BRAKET, RB, SIMM9_8, BRAK… [all …]
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/netbsd/external/gpl3/binutils.old/dist/opcodes/ |
H A D | arc-tbl.h | 16501 { "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { RC, BRAKET, L… 16504 { "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC, BRAKET,… 16507 { "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET,… 16531 { "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, BRAKETdup }, {… 16534 { "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, BRAKETdup }, { … 16537 { "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, SIMM9_8, BRAKE… 16540 { "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, SIMM9_8, BRAKET… 16543 { "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, LIMM, BRAKETdup },… 16546 { "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, LIMM, BRAKETdup }, … 16549 { "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, LL64, { LIMM, BRAKET, RB, SIMM9_8, BRAK… [all …]
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/netbsd/external/gpl3/binutils/dist/opcodes/ |
H A D | arc-tbl.h | 16501 { "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, STORE, NONE, { RC, BRAKET, L… 16504 { "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { RC, BRAKET,… 16507 { "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, STORE, NONE, { W6, BRAKET,… 16531 { "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, BRAKETdup }, {… 16534 { "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, BRAKETdup }, { … 16537 { "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, RB, SIMM9_8, BRAKE… 16540 { "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, RB, SIMM9_8, BRAKET… 16543 { "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { RCD, BRAKET, LIMM, BRAKETdup },… 16546 { "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, STORE, LL64, { W6, BRAKET, LIMM, BRAKETdup }, … 16549 { "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, STORE, LL64, { LIMM, BRAKET, RB, SIMM9_8, BRAK… [all …]
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