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Searched refs:ARAHB_MEM_WRQUE_MST_ID_OFFSET (Results 1 – 10 of 10) sorted by relevance

/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/nvidia/tegra/soc/t210/drivers/se/
H A Dsecurity_engine.c180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
H A Dse_private.h36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU macro
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/nvidia/tegra/soc/t210/drivers/se/
H A Dsecurity_engine.c180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
H A Dse_private.h36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU macro
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/nvidia/tegra/soc/t210/drivers/se/
H A Dsecurity_engine.c180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
H A Dse_private.h36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU macro
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/nvidia/tegra/soc/t210/drivers/se/
H A Dsecurity_engine.c180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
H A Dse_private.h36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU macro
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/nvidia/tegra/soc/t210/drivers/se/
H A Dsecurity_engine.c180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
H A Dse_private.h36 #define ARAHB_MEM_WRQUE_MST_ID_OFFSET 0xFCU macro