Home
last modified time | relevance | path

Searched refs:ASSERT_REG_POSITION (Results 1 – 16 of 16) sorted by relevance

/dports/emulators/citra/citra-ac98458e0/src/video_core/
H A Dregs.h54 ASSERT_REG_POSITION(trigger_irq, 0x10);
56 ASSERT_REG_POSITION(rasterizer, 0x40);
68 ASSERT_REG_POSITION(texturing, 0x80);
70 ASSERT_REG_POSITION(texturing.texture0, 0x81);
77 ASSERT_REG_POSITION(texturing.proctex, 0xa8);
97 ASSERT_REG_POSITION(framebuffer, 0x100);
101 ASSERT_REG_POSITION(lighting, 0x140);
103 ASSERT_REG_POSITION(pipeline, 0x200);
116 ASSERT_REG_POSITION(gs, 0x280);
117 ASSERT_REG_POSITION(vs, 0x2b0);
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/src/video_core/
H A Dregs.h54 ASSERT_REG_POSITION(trigger_irq, 0x10);
56 ASSERT_REG_POSITION(rasterizer, 0x40);
68 ASSERT_REG_POSITION(texturing, 0x80);
70 ASSERT_REG_POSITION(texturing.texture0, 0x81);
77 ASSERT_REG_POSITION(texturing.proctex, 0xa8);
97 ASSERT_REG_POSITION(framebuffer, 0x100);
101 ASSERT_REG_POSITION(lighting, 0x140);
103 ASSERT_REG_POSITION(pipeline, 0x200);
116 ASSERT_REG_POSITION(gs, 0x280);
117 ASSERT_REG_POSITION(vs, 0x2b0);
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/src/video_core/engines/
H A Dmaxwell_3d.h1573 ASSERT_REG_POSITION(macros, 0x45);
1575 ASSERT_REG_POSITION(upload, 0x60);
1579 ASSERT_REG_POSITION(sync_info, 0xB2);
1587 ASSERT_REG_POSITION(rt, 0x200);
1611 ASSERT_REG_POSITION(zeta, 0x3F8);
1631 ASSERT_REG_POSITION(blend, 0x4CF);
1655 ASSERT_REG_POSITION(tsc, 0x557);
1658 ASSERT_REG_POSITION(tic, 0x55D);
1669 ASSERT_REG_POSITION(draw, 0x585);
1685 ASSERT_REG_POSITION(query, 0x6C0);
[all …]
H A Dfermi_2d.h166 ASSERT_REG_POSITION(dst, 0x80);
167 ASSERT_REG_POSITION(src, 0x8C);
168 ASSERT_REG_POSITION(operation, 0xAB);
169 ASSERT_REG_POSITION(blit_control, 0x223);
170 ASSERT_REG_POSITION(blit_dst_x, 0x22c);
171 ASSERT_REG_POSITION(blit_dst_y, 0x22d);
174 ASSERT_REG_POSITION(blit_du_dx, 0x230);
175 ASSERT_REG_POSITION(blit_dv_dy, 0x232);
176 ASSERT_REG_POSITION(blit_src_x, 0x234);
177 ASSERT_REG_POSITION(blit_src_y, 0x236);
[all …]
H A Dmaxwell_dma.h260 ASSERT_REG_POSITION(launch_dma, 0xC0);
261 ASSERT_REG_POSITION(offset_in, 0x100);
262 ASSERT_REG_POSITION(offset_out, 0x102);
263 ASSERT_REG_POSITION(pitch_in, 0x104);
264 ASSERT_REG_POSITION(pitch_out, 0x105);
265 ASSERT_REG_POSITION(line_length_in, 0x106);
266 ASSERT_REG_POSITION(line_count, 0x107);
267 ASSERT_REG_POSITION(remap_const, 0x1C0);
268 ASSERT_REG_POSITION(dst_params, 0x1C3);
269 ASSERT_REG_POSITION(src_params, 0x1CA);
[all …]
H A Dkepler_compute.h249 #define ASSERT_REG_POSITION(field_name, position) \ macro
257 ASSERT_REG_POSITION(upload, 0x60);
258 ASSERT_REG_POSITION(exec_upload, 0x6C);
259 ASSERT_REG_POSITION(data_upload, 0x6D);
260 ASSERT_REG_POSITION(launch, 0xAF);
261 ASSERT_REG_POSITION(tsc, 0x557);
262 ASSERT_REG_POSITION(tic, 0x55D);
263 ASSERT_REG_POSITION(code_loc, 0x582);
264 ASSERT_REG_POSITION(tex_cb_index, 0x982);
272 #undef ASSERT_REG_POSITION
H A Dkepler_memory.h76 #define ASSERT_REG_POSITION(field_name, position) \ macro
80 ASSERT_REG_POSITION(upload, 0x60);
81 ASSERT_REG_POSITION(exec, 0x6C);
82 ASSERT_REG_POSITION(data, 0x6D);
83 #undef ASSERT_REG_POSITION
/dports/emulators/citra/citra-ac98458e0/src/core/hle/applets/
H A Dmii_selector.h38 #define ASSERT_REG_POSITION(field_name, position) \ macro
41 ASSERT_REG_POSITION(title, 0x08);
42 ASSERT_REG_POSITION(show_guest_miis, 0x8C);
43 ASSERT_REG_POSITION(initially_selected_mii_index, 0x90);
44 ASSERT_REG_POSITION(guest_mii_whitelist, 0x94);
45 #undef ASSERT_REG_POSITION
109 #define ASSERT_REG_POSITION(field_name, position) \ macro
112 ASSERT_REG_POSITION(selected_mii_data, 0x0C);
113 ASSERT_REG_POSITION(guest_mii_name, 0x6C);
114 #undef ASSERT_REG_POSITION
/dports/emulators/citra-qt5/citra-ac98458e0/src/core/hle/applets/
H A Dmii_selector.h38 #define ASSERT_REG_POSITION(field_name, position) \ macro
41 ASSERT_REG_POSITION(title, 0x08);
42 ASSERT_REG_POSITION(show_guest_miis, 0x8C);
43 ASSERT_REG_POSITION(initially_selected_mii_index, 0x90);
44 ASSERT_REG_POSITION(guest_mii_whitelist, 0x94);
45 #undef ASSERT_REG_POSITION
109 #define ASSERT_REG_POSITION(field_name, position) \ macro
112 ASSERT_REG_POSITION(selected_mii_data, 0x0C);
113 ASSERT_REG_POSITION(guest_mii_name, 0x6C);
114 #undef ASSERT_REG_POSITION
/dports/emulators/yuzu/yuzu-0b47f7a46/src/video_core/
H A Dgpu.h436 ASSERT_REG_POSITION(semaphore_address, 0x4);
438 ASSERT_REG_POSITION(semaphore_trigger, 0x7);
439 ASSERT_REG_POSITION(reference_count, 0x14);
442 ASSERT_REG_POSITION(fence_value, 0x1C);
443 ASSERT_REG_POSITION(fence_action, 0x1D);
445 ASSERT_REG_POSITION(acquire_mode, 0x100);
446 ASSERT_REG_POSITION(acquire_source, 0x101);
447 ASSERT_REG_POSITION(acquire_active, 0x102);
448 ASSERT_REG_POSITION(acquire_timeout, 0x103);
449 ASSERT_REG_POSITION(acquire_value, 0x104);
[all …]
/dports/emulators/citra/citra-ac98458e0/src/core/hw/
H A Dlcd.h71 #define ASSERT_REG_POSITION(field_name, position) \ macro
75 ASSERT_REG_POSITION(color_fill_top, 0x81);
76 ASSERT_REG_POSITION(backlight_top, 0x90);
77 ASSERT_REG_POSITION(color_fill_bottom, 0x281);
78 ASSERT_REG_POSITION(backlight_bottom, 0x290);
80 #undef ASSERT_REG_POSITION
H A Dgpu.h298 #define ASSERT_REG_POSITION(field_name, position) \ macro
302 ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
303 ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
304 ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
305 ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
306 ASSERT_REG_POSITION(display_transfer_config, 0x00300);
307 ASSERT_REG_POSITION(command_processor_config, 0x00638);
309 #undef ASSERT_REG_POSITION
/dports/emulators/citra-qt5/citra-ac98458e0/src/core/hw/
H A Dlcd.h71 #define ASSERT_REG_POSITION(field_name, position) \ macro
75 ASSERT_REG_POSITION(color_fill_top, 0x81);
76 ASSERT_REG_POSITION(backlight_top, 0x90);
77 ASSERT_REG_POSITION(color_fill_bottom, 0x281);
78 ASSERT_REG_POSITION(backlight_bottom, 0x290);
80 #undef ASSERT_REG_POSITION
H A Dgpu.h298 #define ASSERT_REG_POSITION(field_name, position) \ macro
302 ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
303 ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
304 ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
305 ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
306 ASSERT_REG_POSITION(display_transfer_config, 0x00300);
307 ASSERT_REG_POSITION(command_processor_config, 0x00638);
309 #undef ASSERT_REG_POSITION
/dports/emulators/citra/citra-ac98458e0/src/core/hle/service/hid/
H A Dhid.h183 #define ASSERT_REG_POSITION(field_name, position) \ macro
187 ASSERT_REG_POSITION(pad.index_reset_ticks, 0x0);
188 ASSERT_REG_POSITION(touch.index_reset_ticks, 0x2A);
190 #undef ASSERT_REG_POSITION
/dports/emulators/citra-qt5/citra-ac98458e0/src/core/hle/service/hid/
H A Dhid.h183 #define ASSERT_REG_POSITION(field_name, position) \ macro
187 ASSERT_REG_POSITION(pad.index_reset_ticks, 0x0);
188 ASSERT_REG_POSITION(touch.index_reset_ticks, 0x2A);
190 #undef ASSERT_REG_POSITION