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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/UefiCpuPkg/Include/Register/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/UefiCpuPkg/Include/Register/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/UefiCpuPkg/Include/Register/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/sysutils/edk2/edk2-edk2-stable202102/MdePkg/Include/Register/Intel/
H A DStmStatusCode.h56 #define ERROR_SMM_BAD_BUFFER (BIT31 | BIT17 | 0x0001)
57 #define ERROR_SMM_INVALID_RSC (BIT31 | BIT17 | 0x0004)
58 #define ERROR_SMM_INVALID_BUFFER_SIZE (BIT31 | BIT17 | 0x0005)
59 #define ERROR_SMM_BUFFER_TOO_SHORT (BIT31 | BIT17 | 0x0006)
60 #define ERROR_SMM_INVALID_LIST (BIT31 | BIT17 | 0x0007)
61 #define ERROR_SMM_OUT_OF_MEMORY (BIT31 | BIT17 | 0x0008)
62 #define ERROR_SMM_AFTER_INIT (BIT31 | BIT17 | 0x0009)
63 #define ERROR_SMM_UNSPECIFIED (BIT31 | BIT17 | 0xFFFF)
64 #define ERROR_INVALID_API (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
65 #define ERROR_INVALID_PARAMETER (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dmeminit.c620 …COMPEN1CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT19|BIT17), ((BIT31|BIT30)|BIT19|BIT17… in ddrphy_init()
638 …el_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP… in ddrphy_init()
639 …el_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x0A<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP… in ddrphy_init()
640 …el_i * DDRCOMP_CH_OFFSET)), (BIT31|(0x10<<16)), (BIT31|(BIT20|BIT19|BIT18|BIT17|BIT16))); // DCOMP… in ddrphy_init()
773 … (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (BIT17), (BIT17)); // Enable M… in ddrphy_init()
777 isbM32m(DDRPHY, (ECCMDLLCTL), (BIT17), (BIT17)); // Enable MCDLL in ddrphy_init()
1262 isbM32m(DDRPHY, B0LATCTL0, val << 16, (BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
1273 isbM32m(DDRPHY, B1LATCTL0, val << 16, (BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
1276 isbM32m(DDRPHY, B01LATCTL1, val << 16, (BIT20|BIT19|BIT18|BIT17|BIT16)); in rcvn_cal()
2135 …((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFA… in set_auto_refresh()
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsPmc.h105 #define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
143 #define B_ACPI_IO_SMI_STS_LEGACY_USB2 BIT17
183 #define B_ACPI_IO_GPE_CNTL_SWGPE_CTRL BIT17
224 #define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
253 #define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17
374 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT17
434 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D0 BIT17
474 #define V_PMC_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seco…
475 #define V_PMC_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
619 #define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D3_FDIS_PMC BIT17 ///< PCIe Controller D Port 3 Fu…
[all …]
H A DPchRegsFia.h63 #define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 | BIT17 | BIT16)
71 #define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 | BIT17 | BIT16)
79 #define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 | BIT17 | BIT16)
87 #define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 | BIT17 | BIT16)
H A DPchRegsHsio.h133 #define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
139 #define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
148 #define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
160 …LL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
H A DPchRegsPcie.h145 #define B_PCH_PCIE_CFG_MPC_CCEL (BIT17 | BIT16 | BIT15)
176 #define B_PCH_PCIE_CFG_PWRCTL_WPDMPGEP BIT17
328 #define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17
350 #define B_PCH_PCIE_CFG_EQCFG1_LEP3B BIT17
431 #define B_PCH_PCIE_CFG_EQCFG2_PCET (BIT19 | BIT18 | BIT17 | BIT16)
459 #define B_SPX_PCR_PCD_P2D BIT17 ///< Port 2 disable
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsFia.h45 #define B_PCH_PCR_FIA_CC_PTOCGE BIT17
87 #define B_PCH_PCR_FIA_L4O (BIT19 | BIT18 | BIT17 | BIT16)
95 #define B_PCH_PCR_FIA_L12O (BIT19 | BIT18 | BIT17 | BIT16)
103 #define B_PCH_PCR_FIA_L20O (BIT19 | BIT18 | BIT17 | BIT16)
111 #define B_PCH_PCR_FIA_L28O (BIT19 | BIT18 | BIT17 | BIT16)
H A DPchRegsPmc.h79 #define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at…
110 #define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17
181 #define B_PCH_SMI_EN_LEGACY_USB2 BIT17
219 #define B_PCH_SMI_STS_LEGACY_USB2 BIT17
259 #define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17
426 #define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A#…
427 #define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seco…
428 #define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
492 #define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host W…
598 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fus…
[all …]
H A DPchRegsHsio.h109 #define B_PCH_HSIO_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
115 #define B_PCH_HSIO_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
124 #define B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BI…
153 …LL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/
H A DPchRegsPmc.h80 #define B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK BIT17 ///< Lock ACPI BASE at…
111 #define B_PCH_PMC_BM_CX_CNF_XHCI_BREAK_EN BIT17
182 #define B_PCH_SMI_EN_LEGACY_USB2 BIT17
220 #define B_PCH_SMI_STS_LEGACY_USB2 BIT17
260 #define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL BIT17
427 #define B_PCH_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A#…
428 #define V_PCH_PWRM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seco…
429 #define V_PCH_PWRM_CFG_SAMAW_98ms BIT17 ///< 98ms
493 #define B_PCH_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host W…
599 #define B_PCH_PWRM_FUSE_DIS_RD_1_PCIE_D3_FUSE_DIS BIT17 ///< PCIe Controller D Port 3 Fus…
[all …]
/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/drivers/renesas/common/emmc/
H A Demmc_interrupt.c32 end_bit = BIT17; in emmc_interrupt()
34 end_bit = BIT17; in emmc_interrupt()
40 end_bit = BIT17; in emmc_interrupt()
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { in emmc_interrupt()
/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/drivers/renesas/common/emmc/
H A Demmc_interrupt.c32 end_bit = BIT17; in emmc_interrupt()
34 end_bit = BIT17; in emmc_interrupt()
40 end_bit = BIT17; in emmc_interrupt()
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { in emmc_interrupt()
/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/drivers/renesas/common/emmc/
H A Demmc_interrupt.c32 end_bit = BIT17; in emmc_interrupt()
34 end_bit = BIT17; in emmc_interrupt()
40 end_bit = BIT17; in emmc_interrupt()
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { in emmc_interrupt()
/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/drivers/renesas/common/emmc/
H A Demmc_interrupt.c32 end_bit = BIT17; in emmc_interrupt()
34 end_bit = BIT17; in emmc_interrupt()
40 end_bit = BIT17; in emmc_interrupt()
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { in emmc_interrupt()
/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/drivers/renesas/common/emmc/
H A Demmc_interrupt.c32 end_bit = BIT17; in emmc_interrupt()
34 end_bit = BIT17; in emmc_interrupt()
40 end_bit = BIT17; in emmc_interrupt()
138 if ((BIT17 & mmc_drv_obj.dm_event2) != 0) { in emmc_interrupt()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Include/Guid/
H A DBoardFeatures.h62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
65 #define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
159 #define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/
H A DBoardFeatures.h50 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
53 #define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
144 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
147 #define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17

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