1 /** @file 2 Register definition for FIA component 3 4 Conventions: 5 6 - Register definition format: 7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName 8 - Prefix: 9 Definitions beginning with "R_" are registers 10 Definitions beginning with "B_" are bits within registers 11 Definitions beginning with "V_" are meaningful values within the bits 12 Definitions beginning with "S_" are register size 13 Definitions beginning with "N_" are the bit position 14 - [GenerationName]: 15 Three letter acronym of the generation is used . 16 Register name without GenerationName applies to all generations. 17 - [ComponentName]: 18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) 19 Register name without ComponentName applies to all components. 20 Register that is specific to -H denoted by "_PCH_H_" in component name. 21 Register that is specific to -LP denoted by "_PCH_LP_" in component name. 22 - SubsystemName: 23 This field indicates the subsystem name of the component that the register belongs to 24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.). 25 - RegisterSpace: 26 MEM - MMIO space register of subsystem. 27 IO - IO space register of subsystem. 28 PCR - Private configuration register of subsystem. 29 CFG - PCI configuration space register of subsystem. 30 - RegisterName: 31 Full register name. 32 33 Copyright (c) 2019 Intel Corporation. All rights reserved. <BR> 34 35 SPDX-License-Identifier: BSD-2-Clause-Patent 36 **/ 37 38 #ifndef _PCH_REGS_FIA_H_ 39 #define _PCH_REGS_FIA_H_ 40 41 42 // 43 // Private chipset register (Memory space) offset definition 44 // The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well. 45 // 46 47 // 48 // PCH FIA lane owner encoding 49 // 50 #define V_PCH_FIA_PCR_LANE_OWN_PCIEDMI 0x0 51 #define V_PCH_FIA_PCR_LANE_OWN_USB3 0x1 52 #define V_PCH_FIA_PCR_LANE_OWN_SATA 0x2 53 #define V_PCH_FIA_PCR_LANE_OWN_GBE 0x3 54 #define V_PCH_FIA_PCR_LANE_OWN_MOBEXP 0x4 55 #define V_PCH_FIA_PCR_LANE_OWN_SSIC 0x5 56 #define V_PCH_FIA_PCR_LANE_OWN_CSI3 0x6 57 #define V_PCH_FIA_PCR_LANE_OWN_UFS 0x7 58 59 #define B_PCH_FIA_PCR_L0O (BIT3 | BIT2 | BIT1 | BIT0) 60 #define B_PCH_FIA_PCR_L1O (BIT7 | BIT6 | BIT5 | BIT4) 61 #define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 | BIT9 | BIT8) 62 #define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 | BIT13 | BIT12) 63 #define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 | BIT17 | BIT16) 64 #define B_PCH_FIA_PCR_L5O (BIT23 | BIT22 | BIT21 | BIT20) 65 #define B_PCH_FIA_PCR_L6O (BIT27 | BIT26 | BIT25 | BIT24) 66 #define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 | BIT29 | BIT28) 67 #define B_PCH_FIA_PCR_L8O (BIT3 | BIT2 | BIT1 | BIT0) 68 #define B_PCH_FIA_PCR_L9O (BIT7 | BIT6 | BIT5 | BIT4) 69 #define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 | BIT9 | BIT8) 70 #define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 | BIT13 | BIT12) 71 #define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 | BIT17 | BIT16) 72 #define B_PCH_FIA_PCR_L13O (BIT23 | BIT22 | BIT21 | BIT20) 73 #define B_PCH_FIA_PCR_L14O (BIT27 | BIT26 | BIT25 | BIT24) 74 #define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 | BIT29 | BIT28) 75 #define B_PCH_FIA_PCR_L16O (BIT3 | BIT2 | BIT1 | BIT0) 76 #define B_PCH_FIA_PCR_L17O (BIT7 | BIT6 | BIT5 | BIT4) 77 #define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 | BIT9 | BIT8) 78 #define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 | BIT13 | BIT12) 79 #define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 | BIT17 | BIT16) 80 #define B_PCH_FIA_PCR_L21O (BIT23 | BIT22 | BIT21 | BIT20) 81 #define B_PCH_FIA_PCR_L22O (BIT27 | BIT26 | BIT25 | BIT24) 82 #define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 | BIT29 | BIT28) 83 #define B_PCH_FIA_PCR_L24O (BIT3 | BIT2 | BIT1 | BIT0) 84 #define B_PCH_FIA_PCR_L25O (BIT7 | BIT6 | BIT5 | BIT4) 85 #define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 | BIT9 | BIT8) 86 #define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 | BIT13 | BIT12) 87 #define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 | BIT17 | BIT16) 88 #define B_PCH_FIA_PCR_L29O (BIT23 | BIT22 | BIT21 | BIT20) 89 90 #endif 91