/dports/math/primecount/primecount-7.2/lib/primesieve/src/ |
H A D | LookupTables.cpp | 106 { BIT6, 2, 1, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, -7 }, 108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 }, 109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 }, 112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 }, 113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 }, 115 { BIT5, 6, 5, 1 }, { BIT1, 4, 3, 1 }, { BIT2, 2, 1, 1 }, { BIT6, 4, 3, 1 }, 118 { BIT2, 2, 2, 1 }, { BIT1, 4, 4, 1 }, { BIT0, 6, 5, 1 }, { BIT7, 2, 2, -7 }, 119 { BIT7, 6, 1, 1 }, { BIT0, 4, 0, 1 }, { BIT1, 2, 0, 1 }, { BIT2, 4, 0, 1 }, 126 { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, 1 }, { BIT0, 6, 1, 1 }, 129 { BIT3, 2, 0, 1 }, { BIT7, 6, 2, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, [all …]
|
H A D | EratSmall.cpp | 119 p[sievingPrime * 18 + 4] &= BIT2; in crossOff() 128 case 5: CHECK_FINISHED(5); *p &= BIT2; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff() 145 p[sievingPrime * 22 + 8] &= BIT2; in crossOff() 154 case 14: CHECK_FINISHED(14); *p &= BIT2; p += sievingPrime * 6 + 2; FALLTHROUGH; in crossOff() 164 p[sievingPrime * 0 + 0] &= BIT2; in crossOff() 196 p[sievingPrime * 28 + 16] &= BIT2; in crossOff() 205 case 31: CHECK_FINISHED(31); *p &= BIT2; p += sievingPrime * 2 + 1; in crossOff() 215 p[sievingPrime * 6 + 4] &= BIT2; in crossOff() 241 p[sievingPrime * 10 + 8] &= BIT2; in crossOff() 268 p[sievingPrime * 16 + 16] &= BIT2; in crossOff() [all …]
|
/dports/math/primesieve/primesieve-7.7/src/ |
H A D | LookupTables.cpp | 106 { BIT6, 2, 1, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, -7 }, 108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 }, 109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 }, 112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 }, 113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 }, 115 { BIT5, 6, 5, 1 }, { BIT1, 4, 3, 1 }, { BIT2, 2, 1, 1 }, { BIT6, 4, 3, 1 }, 118 { BIT2, 2, 2, 1 }, { BIT1, 4, 4, 1 }, { BIT0, 6, 5, 1 }, { BIT7, 2, 2, -7 }, 119 { BIT7, 6, 1, 1 }, { BIT0, 4, 0, 1 }, { BIT1, 2, 0, 1 }, { BIT2, 4, 0, 1 }, 126 { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, 1 }, { BIT0, 6, 1, 1 }, 129 { BIT3, 2, 0, 1 }, { BIT7, 6, 2, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, [all …]
|
H A D | EratSmall.cpp | 119 p[sievingPrime * 18 + 4] &= BIT2; in crossOff() 128 case 5: CHECK_FINISHED(5); *p &= BIT2; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff() 145 p[sievingPrime * 22 + 8] &= BIT2; in crossOff() 154 case 14: CHECK_FINISHED(14); *p &= BIT2; p += sievingPrime * 6 + 2; FALLTHROUGH; in crossOff() 164 p[sievingPrime * 0 + 0] &= BIT2; in crossOff() 196 p[sievingPrime * 28 + 16] &= BIT2; in crossOff() 205 case 31: CHECK_FINISHED(31); *p &= BIT2; p += sievingPrime * 2 + 1; in crossOff() 215 p[sievingPrime * 6 + 4] &= BIT2; in crossOff() 241 p[sievingPrime * 10 + 8] &= BIT2; in crossOff() 268 p[sievingPrime * 16 + 16] &= BIT2; in crossOff() [all …]
|
/dports/math/scilab/scilab-6.1.1/scilab/modules/integer/src/c/ |
H A D | genbitops.c | 18 #define BIT2(Type,Op) {\ macro 71 BIT2(integer1, | ); in C2F() 74 BIT2(integer2, | ); in C2F() 77 BIT2(integer, | ); in C2F() 80 BIT2(unsigned char, | ); in C2F() 86 BIT2(unsigned int, | ); in C2F() 94 BIT2(integer1, &); in C2F() 97 BIT2(integer2, &); in C2F() 100 BIT2(integer, &); in C2F() 103 BIT2(unsigned char, &); in C2F() [all …]
|
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 147 #define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range 159 #define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range 166 #define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range 206 #define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable 507 #define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 635 #define B_PCH_ACPI_GPE_CNTL_PCIE2_SCI_EN BIT2 796 #define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2) 867 #define B_PCH_PMC_PSS_PG_STS_HDA BIT2 // HDA 904 #define B_PCH_PMC_D3_STS_1_OTG_SS BIT2 // OTG SS 941 #define B_PCH_PMC_D3_STDBY_STS_1_OTG_SS BIT2 // OTG SS [all …]
|
H A D | PchRegsLpss.h | 67 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable 86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type 93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type 171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type 178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type 258 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type 265 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type 345 #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type 352 #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type 437 #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
H A D | PchRegsPcu.h | 141 #define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range 153 #define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range 160 #define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range 200 #define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable 501 #define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 629 #define B_PCH_ACPI_GPE_CNTL_PCIE2_SCI_EN BIT2 790 #define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2) 861 #define B_PCH_PMC_PSS_PG_STS_HDA BIT2 // HDA 898 #define B_PCH_PMC_D3_STS_1_OTG_SS BIT2 // OTG SS 935 #define B_PCH_PMC_D3_STDBY_STS_1_OTG_SS BIT2 // OTG SS [all …]
|
H A D | PchRegsLpss.h | 61 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable 80 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type 87 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type 165 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type 172 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type 252 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type 259 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type 339 #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type 346 #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type 431 #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsLpc.h | 55 #define B_LPC_CFG_SERIRQ_CNT_SIRQSZ (BIT5 | BIT4 | BIT3 | BIT2) 83 #define B_LPC_CFG_IOD_COMA (BIT2 | BIT1 | BIT0) 122 #define B_LPC_CFG_ULKMC_64REN BIT2 159 #define B_LPC_CFG_BDE_60 BIT2 172 #define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP BIT2 215 #define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap 223 #define B_ESPI_SLAVE_BME BIT2 ///< Bus Master Enable 234 #define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2 245 #define B_PCH_IO_RST_CNT_RST_CPU BIT2 285 #define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable [all …]
|
H A D | PchRegsPmc.h | 92 #define B_ACPI_IO_PM1_CNT_GBL_RLS BIT2 114 #define B_ACPI_IO_SMI_EN_BIOS BIT2 157 #define B_ACPI_IO_SMI_STS_BIOS BIT2 235 #define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 262 #define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 289 #define B_TCO_IO_TCO1_STS_TCO_INT BIT2 301 #define B_TCO_IO_TCO2_STS_BOOT BIT2 401 #define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2 449 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A2 BIT2 561 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) [all …]
|
H A D | PchRegsSata.h | 97 #define B_SATA_CFG_AHCI_BAR_TP (BIT2 | BIT1) 161 #define B_SATA_CFG_MAP_PORT2_PCD BIT2 178 #define B_SATA_CFG_PCS_P2E BIT2 270 #define B_SATA_CFG_BFCS_BIST_FIS_P BIT2 330 #define B_SATA_MEM_AHCI_GHC_MRSM BIT2 340 #define B_SATA_MEM_AHCI_IS_PORT2 BIT2 350 #define B_SATA_MEM_PORT2_IMPLEMENTED BIT2 388 #define B_SATA_MEM_AHCI_SFM_R10E BIT2 450 #define B_SATA_MEM_AHCI_PXIS_DSS BIT2 475 #define B_SATA_MEM_AHCI_PXIE_DSE BIT2 [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/ |
H A D | Fip006Reg.h | 68 #define TXF_TFOS BIT2 77 #define TXE_TFOE BIT2 86 #define TXC_TFOC BIT2 95 #define RXF_RFOS BIT2 104 #define RXE_RFOE BIT2 113 #define RXC_RFOC BIT2 120 #define FAULTF_PVFS BIT2 127 #define FAULTC_PVFC BIT2 132 #define DM_CFG_MSTARTEN BIT2 148 #define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0) [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Include/ |
H A D | PcieRegs.h | 78 #define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Suppor… 84 #define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable 92 #define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected 109 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed 158 #define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable 176 #define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeo… 185 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed 194 #define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful 284 #define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported 300 #define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2) [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Include/ |
H A D | PcieRegs.h | 79 #define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Suppor… 85 #define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable 93 #define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected 110 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed 159 #define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable 177 #define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeo… 186 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed 195 #define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful 298 #define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported 316 #define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2) [all …]
|
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/ |
H A D | hilFpgaAccess.c | 63 P1DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init() 64 P1SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init() 75 P2DIR |= (BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init() 76 P2SEL &= ~(BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init() 87 P3DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init() 88 P3SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init() 100 P4SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init() 111 P5DIR |= (BIT1+BIT2+BIT4+BIT5); // set pins initially to output direction in hil_fpga_init() 114 P5OUT &= ~(BIT2+BIT4); in hil_fpga_init() 137 P9OUT |= BIT0+BIT1+BIT2+BIT4; in hil_fpga_init() [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsSata.h | 150 #define B_PCH_LP_SATA_PCS_P2E BIT2 180 #define B_PCH_H_SATA_MAP_PORT2_PCD BIT2 198 #define B_PCH_H_SATA_PCS_P2E BIT2 291 #define B_PCH_SATA_BFCS_BIST_FIS_P BIT2 352 #define B_PCH_SATA_AHCI_GHC_MRSM BIT2 362 #define B_PCH_SATA_AHCI_IS_PORT2 BIT2 373 #define B_PCH_SATA_PORT2_IMPLEMENTED BIT2 412 #define B_PCH_SATA_AHCI_RSTF_R10E BIT2 474 #define B_PCH_SATA_AHCI_PXIS_DSS BIT2 499 #define B_PCH_SATA_AHCI_PXIE_DSE BIT2 [all …]
|
H A D | PchRegsPmc.h | 44 #define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI … 102 #define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 168 #define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 190 #define B_PCH_SMI_EN_BIOS BIT2 233 #define B_PCH_SMI_STS_BIOS BIT2 309 #define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 335 #define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 362 #define B_PCH_TCO1_STS_TCO_INT BIT2 376 #define B_PCH_TCO2_STS_BOOT BIT2 509 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
H A D | PchRegsPmc.h | 45 #define B_PCH_PMC_ACPI_CNT_SCIS (BIT2 | BIT1 | BIT0) ///< SCI … 103 #define B_PCH_PMC_GEN_PMCON_B_RTC_PWR_STS BIT2 169 #define B_PCH_ACPI_PM1_CNT_GBL_RLS BIT2 191 #define B_PCH_SMI_EN_BIOS BIT2 234 #define B_PCH_SMI_STS_BIOS BIT2 310 #define B_PCH_ACPI_GPE0_STS_127_96_SWGPE BIT2 336 #define B_PCH_ACPI_GPE0_EN_127_96_SWGPE BIT2 363 #define B_PCH_TCO1_STS_TCO_INT BIT2 377 #define B_PCH_TCO2_STS_BOOT BIT2 510 #define B_PCH_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) [all …]
|
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/ |
H A D | PcieRegs.h | 46 #define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Suppor… 60 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed 93 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed 127 #define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported 147 #define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2) 148 #define B_PCI_BAR_MEMORY_TYPE_64 BIT2
|
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdePkg/Include/IndustryStandard/ |
H A D | TpmPtp.h | 178 #define PTP_FIFO_ACC_PENDIND BIT2 212 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 223 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 226 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 388 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 415 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
|
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdePkg/Include/IndustryStandard/ |
H A D | TpmPtp.h | 178 #define PTP_FIFO_ACC_PENDIND BIT2 212 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 223 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 226 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 388 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 415 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
|
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdePkg/Include/IndustryStandard/ |
H A D | TpmPtp.h | 178 #define PTP_FIFO_ACC_PENDIND BIT2 212 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 223 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 226 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 388 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 415 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
|
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdePkg/Include/IndustryStandard/ |
H A D | TpmPtp.h | 178 #define PTP_FIFO_ACC_PENDIND BIT2 212 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 223 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 226 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 388 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 415 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
|
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdePkg/Include/IndustryStandard/ |
H A D | TpmPtp.h | 178 #define PTP_FIFO_ACC_PENDIND BIT2 212 #define PTP_FIFO_STS_SELFTEST_DONE BIT2 223 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3) 226 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2) 384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4) 386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2) 388 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3) 415 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
|