/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/OvmfPkg/Include/IndustryStandard/ |
H A D | LsiScsi.h | 87 #define LSI_INS_BLK_SCSIP_CMD BIT25 88 #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25) 89 #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26) 90 #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26) 103 #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/OvmfPkg/Include/IndustryStandard/ |
H A D | LsiScsi.h | 87 #define LSI_INS_BLK_SCSIP_CMD BIT25 88 #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25) 89 #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26) 90 #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26) 103 #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/OvmfPkg/Include/IndustryStandard/ |
H A D | LsiScsi.h | 87 #define LSI_INS_BLK_SCSIP_CMD BIT25 88 #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25) 89 #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26) 90 #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26) 103 #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/OvmfPkg/Include/IndustryStandard/ |
H A D | LsiScsi.h | 87 #define LSI_INS_BLK_SCSIP_CMD BIT25 88 #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25) 89 #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26) 90 #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26) 103 #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)
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/dports/sysutils/edk2/edk2-edk2-stable202102/OvmfPkg/Include/IndustryStandard/ |
H A D | LsiScsi.h | 87 #define LSI_INS_BLK_SCSIP_CMD BIT25 88 #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25) 89 #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26) 90 #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26) 103 #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsFia.h | 65 #define B_PCH_FIA_PCR_L6O (BIT27 | BIT26 | BIT25 | BIT24) 73 #define B_PCH_FIA_PCR_L14O (BIT27 | BIT26 | BIT25 | BIT24) 81 #define B_PCH_FIA_PCR_L22O (BIT27 | BIT26 | BIT25 | BIT24)
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H A D | PchRegsPmc.h | 205 #define B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS BIT25 366 #define B_PMC_PWRM_GEN_PMCON_A_MPHY_CRICLK_GATE_OVR BIT25 426 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_DMI BIT25 463 #define B_PMC_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow … 531 #define B_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) 612 #define B_PMC_PWRM_NST_PG_FDIS_1_SMBUS_FDIS_PMC BIT25 ///< Smbus Function Disable 638 #define B_PMC_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
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H A D | PchRegsPcie.h | 141 #define B_PCH_PCIE_CFG_MPC_IRRCE BIT25 197 #define B_PCH_PCIE_CFG_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24) 277 #define B_PCH_PCIE_CFG_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) 404 #define B_PCH_PCIE_CFG_LTCO1_L1TCOE BIT25 416 #define B_PCH_PCIE_CFG_LTCO2_L3TCOE BIT25
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/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/sysutils/edk2/edk2-edk2-stable202102/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
H A D | FdtPciPcdProducerLib.c | 35 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25 36 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24) 38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
H A D | PchRegsFia.h | 89 #define B_PCH_PCR_FIA_L6O (BIT27 | BIT26 | BIT25 | BIT24) 97 #define B_PCH_PCR_FIA_L14O (BIT27 | BIT26 | BIT25 | BIT24) 105 #define B_PCH_PCR_FIA_L22O (BIT27 | BIT26 | BIT25 | BIT24)
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H A D | PchRegsPcie.h | 181 #define B_PCH_PCIE_MPC_IRRCE BIT25 237 #define B_PCH_PCIE_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24) 317 #define B_PCH_PCIE_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) 427 #define B_PCH_PCIE_LTCO1_L1TCOE BIT25 439 #define B_PCH_PCIE_LTCO2_L3TCOE BIT25
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H A D | PchRegsSata.h | 154 #define B_PCH_LP_SATA_SCLKGC_PCD (BIT26 | BIT25 | BIT24) 156 #define B_PCH_LP_SATA_SCLKGC_PORT1_PCD BIT25 331 #define B_PCH_SATA_AHCI_CAP_SAL BIT25 384 #define B_PCH_SATA_AHCI_EM_CTRL_ATTR_XMT BIT25 514 #define B_PCH_SATA_AHCI_PxCMD_DLAE BIT25 612 #define B_PCH_SATA_AHCI_PXSERR_UN_FIS_TYPE BIT25
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H A D | PchRegsPmc.h | 281 #define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 419 #define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow … 481 #define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) 521 #define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24)… 576 #define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This i… 616 #define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
H A D | general_definitions.h | 36 #undef BIT25 72 #define BIT25 0x02000000U macro
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
H A D | PchRegsPmc.h | 282 #define B_PCH_OC_WDT_CTL_ICCSURV_STS BIT25 420 #define B_PCH_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow … 482 #define B_PCH_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) 522 #define B_PCH_PWRM_MODPHY_PM_CFG2_EFRT (BIT28 | BIT27 | BIT26 | BIT25 | BIT24)… 577 #define B_PCH_PWRM_NST_PG_FDIS_1_SCC_FDIS_PMC BIT25 ///< SCC Function Disable. This i… 617 #define B_PCH_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC Fuse Disable
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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2TbltDevicePkg/Include/Guid/ |
H A D | BoardFeatures.h | 76 #define B_BOARD_FEATURES_SLEEP_MASK BIT25 78 #define V_BOARD_FEATURES_SLEEP_S3 BIT25 // BIT25=1 170 #define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2 Channel 0 memory slot
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/Vlv2TbltDevicePkg/Include/Guid/ |
H A D | BoardFeatures.h | 64 #define B_BOARD_FEATURES_SLEEP_MASK BIT25 66 #define V_BOARD_FEATURES_SLEEP_S3 BIT25 // BIT25=1 158 #define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2 Channel 0 memory slot
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