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Searched refs:BIT29 (Results 1 – 25 of 313) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_BB.c284 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
318 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
321 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
553 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
586 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
589 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
H A DHalHWImg8723B_MAC.c255 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
286 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
289 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
H A DHalHWImg8723B_RF.c286 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
320 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
323 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_BB.c284 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
318 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
321 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
553 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
586 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
589 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
H A DHalHWImg8723B_MAC.c255 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
286 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
289 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
H A DHalHWImg8723B_RF.c286 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
320 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
323 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_BB.c284 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
318 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
321 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_AGC_TAB()
553 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
586 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
589 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_PHY_REG()
H A DHalHWImg8723B_MAC.c255 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
286 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
289 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_MAC_REG()
H A DHalHWImg8723B_RF.c286 u8 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
320 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
323 cCond = (u8)((v1 & (BIT29|BIT28)) >> 28); in ODM_ReadAndConfig_MP_8723B_RadioA()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsFia.h61 #define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28)
90 #define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28)
98 #define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28)
106 #define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28)
H A DPchRegsHsio.h48 #define B_PCH_HSIO_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29
65 #define B_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 …
99 #define B_PCH_HSIO_RX_DWORD57_JIM_ENABLE BIT29
122 #define B_PCH_HSIO_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BI…
H A DPchRegsPcie.h342 #define B_PCH_PCIE_PCIESTS2_P2PNCCWSSCMES BIT29
348 #define B_PCH_PCIE_PCIEALC_ITLRCLD BIT29
409 #define B_PCH_PCIE_FOMS_I (BIT30 | BIT29)
422 #define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsHsio.h74 #define B_HSIO_PCR_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29
89 #define B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 …
123 #define B_HSIO_PCR_RX_DWORD57_JIM_ENABLE BIT29
146 #define B_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BI…
H A DPchRegsFia.h66 #define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 | BIT29 | BIT28)
74 #define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 | BIT29 | BIT28)
82 #define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 | BIT29 | BIT28)
H A DPchRegsPcie.h302 #define B_PCH_PCIE_CFG_PCIESTS2_P2PNCCWSSCMES BIT29
308 #define B_PCH_PCIE_CFG_PCIEALC_ITLRCLD BIT29
386 #define B_PCH_PCIE_CFG_FOMS_I (BIT30 | BIT29)
399 #define B_PCH_PCIE_CFG_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsLpss.h61 #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
146 #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
233 #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
320 #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
412 #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsLpss.h55 #define B_PCH_LPSS_DMAC_STSCMD_RMA BIT29 // RMA
140 #define B_PCH_LPSS_I2C_STSCMD_RMA BIT29 // RMA
227 #define B_PCH_LPSS_PWM_STSCMD_RMA BIT29 // RMA
314 #define B_PCH_LPSS_HSUART_STSCMD_RMA BIT29 // RMA
406 #define B_PCH_LPSS_SPI_STSCMD_RMA BIT29 // RMA
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
H A Dgeneral_definitions.h40 #undef BIT29
76 #define BIT29 0x20000000U macro
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/
H A DFdtPciPcdProducerLib.c34 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)

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