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/dports/math/primecount/primecount-7.2/lib/primesieve/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
107 { BIT1, 6, 2, 1 }, { BIT3, 4, 1, 1 }, { BIT7, 2, 1, 1 }, { BIT5, 4, 2, 1 },
110 { BIT1, 2, 1, 1 }, { BIT0, 4, 1, 1 }, { BIT6, 6, 3, 1 }, { BIT3, 2, 1, -7 },
111 { BIT3, 6, 3, 1 }, { BIT6, 4, 3, 1 }, { BIT0, 2, 1, 1 }, { BIT1, 4, 2, 1 },
114 { BIT5, 2, 1, 1 }, { BIT7, 4, 3, 1 }, { BIT3, 6, 4, 1 }, { BIT1, 2, 1, -7 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp116 p[sievingPrime * 10 + 2] &= BIT3; in crossOff()
125 case 2: CHECK_FINISHED(2); *p &= BIT3; p += sievingPrime * 2 + 0; FALLTHROUGH; in crossOff()
140 p[sievingPrime * 6 + 2] &= BIT3; in crossOff()
149 case 9: CHECK_FINISHED( 9); *p &= BIT3; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
171 p[sievingPrime * 28 + 12] &= BIT3; in crossOff()
180 case 23: CHECK_FINISHED(23); *p &= BIT3; p += sievingPrime * 2 + 1; in crossOff()
189 p[sievingPrime * 0 + 0] &= BIT3; in crossOff()
220 p[sievingPrime * 22 + 14] &= BIT3; in crossOff()
244 p[sievingPrime * 18 + 14] &= BIT3; in crossOff()
267 p[sievingPrime * 12 + 12] &= BIT3; in crossOff()
[all …]
/dports/math/primesieve/primesieve-7.7/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
107 { BIT1, 6, 2, 1 }, { BIT3, 4, 1, 1 }, { BIT7, 2, 1, 1 }, { BIT5, 4, 2, 1 },
110 { BIT1, 2, 1, 1 }, { BIT0, 4, 1, 1 }, { BIT6, 6, 3, 1 }, { BIT3, 2, 1, -7 },
111 { BIT3, 6, 3, 1 }, { BIT6, 4, 3, 1 }, { BIT0, 2, 1, 1 }, { BIT1, 4, 2, 1 },
114 { BIT5, 2, 1, 1 }, { BIT7, 4, 3, 1 }, { BIT3, 6, 4, 1 }, { BIT1, 2, 1, -7 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp116 p[sievingPrime * 10 + 2] &= BIT3; in crossOff()
125 case 2: CHECK_FINISHED(2); *p &= BIT3; p += sievingPrime * 2 + 0; FALLTHROUGH; in crossOff()
140 p[sievingPrime * 6 + 2] &= BIT3; in crossOff()
149 case 9: CHECK_FINISHED( 9); *p &= BIT3; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
171 p[sievingPrime * 28 + 12] &= BIT3; in crossOff()
180 case 23: CHECK_FINISHED(23); *p &= BIT3; p += sievingPrime * 2 + 1; in crossOff()
189 p[sievingPrime * 0 + 0] &= BIT3; in crossOff()
220 p[sievingPrime * 22 + 14] &= BIT3; in crossOff()
244 p[sievingPrime * 18 + 14] &= BIT3; in crossOff()
267 p[sievingPrime * 12 + 12] &= BIT3; in crossOff()
[all …]
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsLpss.h85 #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
92 #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
121 #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
170 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
177 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
206 #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
257 #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
264 #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
344 #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
351 #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
[all …]
H A DPchRegsPcu.h146 #define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable
158 #define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable
165 #define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable
260 #define B_PCH_ILB_MC_DRTC BIT3 // Disable RTC
450 #define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3
634 #define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3
648 #define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout
796 #define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2)
903 #define B_PCH_PMC_D3_STS_1_DFX BIT3 // DFX
940 #define B_PCH_PMC_D3_STDBY_STS_1_DFX BIT3 // DFX
[all …]
H A DPchRegsSata.h74 #define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable
88 #define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status
93 #define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable
144 #define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable
162 #define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset
196 #define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled
205 #define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsLpss.h79 #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable
86 #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable
115 #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset
164 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable
171 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable
200 #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset
251 #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable
258 #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable
338 #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable
345 #define B_PCH_LPSS_HSUART_BAR1_PF BIT3 // Prefetchable
[all …]
H A DPchRegsPcu.h140 #define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable
152 #define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable
159 #define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable
166 #define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable
444 #define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3
628 #define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3
642 #define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout
790 #define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2)
897 #define B_PCH_PMC_D3_STS_1_DFX BIT3 // DFX
934 #define B_PCH_PMC_D3_STDBY_STS_1_DFX BIT3 // DFX
[all …]
H A DPchRegsSata.h68 #define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable
82 #define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status
87 #define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable
138 #define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable
156 #define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset
190 #define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled
199 #define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Include/
H A DPcieRegs.h83 #define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable
91 #define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected
109 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
148 #define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable
153 #define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed
157 #define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
185 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
193 #define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful
204 #define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
212 #define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Include/
H A DPcieRegs.h84 #define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable
92 #define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected
110 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
149 #define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable
154 #define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed
158 #define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
186 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
194 #define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful
205 #define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
213 #define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/
H A DFip006Reg.h67 #define TXF_TFUS BIT3
76 #define TXE_TFUE BIT3
85 #define TXC_TFUC BIT3
94 #define RXF_RFUS BIT3
103 #define RXE_RFUE BIT3
112 #define RXC_RFUC BIT3
119 #define FAULTF_DWCBSFS BIT3
126 #define FAULTC_DWCBSFC BIT3
148 #define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0)
165 #define FIFO_CFG_RXFTH (BIT3 | BIT2 | BIT1 | BIT0)
/dports/mail/spambnc/usr/local/sb/dangerous/aaaworking/
H A Dcidrmatch-procmail.rc93 BIT3=8
103 { BIT3=0 }
199 * $ ${BIT3}^0
213 * $ ${BIT3}^0
228 * $ ${BIT3}^0
321 BIT3=8
331 { BIT3=0 }
424 * $ ${BIT3}^0
438 * $ ${BIT3}^0
546 BIT3=8
[all …]
/dports/mail/spambnc/usr/local/sb/functions/
H A Dcidrmatch.rc98 BIT3=8
108 { BIT3=0 }
204 * $ ${BIT3}^0
218 * $ ${BIT3}^0
233 * $ ${BIT3}^0
326 BIT3=8
336 { BIT3=0 }
429 * $ ${BIT3}^0
443 * $ ${BIT3}^0
551 BIT3=8
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h48 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disabl…
54 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL …
63 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 int…
83 …AB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:…
84 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
87 … PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04…
94 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
98 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
104 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
114 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h48 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disabl…
54 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL …
63 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 int…
83 …AB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:…
84 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
87 … PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04…
94 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
98 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
104 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
114 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h48 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disabl…
54 …PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL …
63 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 int…
83 …AB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:…
84 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
87 … PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04…
94 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
98 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
104 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
114 …{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3…
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/
H A DhilFpgaAccess.c63 P1DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
64 P1SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
75 P2DIR |= (BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
76 P2SEL &= ~(BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
87 P3DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
88 P3SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
99 P4DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
100 P4SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
138 P9OUT &= ~(BIT3); in hil_fpga_init()
140 P9DIR &= ~(BIT3); in hil_fpga_init()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
176 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
479 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
511 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
520 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
176 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
479 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
511 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
520 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h35 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
110 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
176 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
202 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
479 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
511 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
520 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsSata.h96 #define B_SATA_CFG_AHCI_BAR_PF BIT3
113 #define B_SATA_CFG_PC_PME_CLK BIT3
118 #define B_SATA_CFG_PMCS_NSFRST BIT3
160 #define B_SATA_CFG_MAP_PORT3_PCD BIT3
177 #define B_SATA_CFG_PCS_P3E BIT3
269 #define B_SATA_CFG_BFCS_BIST_FIS_F BIT3
339 #define B_SATA_MEM_AHCI_IS_PORT3 BIT3
349 #define B_SATA_MEM_PORT3_IMPLEMENTED BIT3
373 #define B_SATA_MEM_AHCI_CAP2_SDS BIT3
387 #define B_SATA_MEM_AHCI_SFM_R5E BIT3
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsSata.h82 #define B_PCH_SATA_AHCI_BAR_PF BIT3
99 #define B_PCH_SATA_PC_PME_CLK BIT3
104 #define B_PCH_SATA_PMCS_NSFRST BIT3
179 #define B_PCH_H_SATA_MAP_PORT3_PCD BIT3
197 #define B_PCH_H_SATA_PCS_P3E BIT3
290 #define B_PCH_SATA_BFCS_BIST_FIS_F BIT3
361 #define B_PCH_SATA_AHCI_IS_PORT3 BIT3
372 #define B_PCH_SATA_PORT3_IMPLEMENTED BIT3
396 #define B_PCH_SATA_AHCI_CAP2_SDS BIT3
411 #define B_PCH_SATA_AHCI_RSTF_R5E BIT3
[all …]
H A DPchRegsScs.h61 #define B_PCH_SCS_DEV_PCS_NSS BIT3 ///< No Soft Reset
65 #define B_PCH_SCS_DEV_PG_CONFIG_SE BIT3 ///< Sleep Enable
80 #define B_PCH_SCS_DEV_MEM_XFRMODE_AUTOCMD_EN_MASK (BIT2 | BIT3)
90 #define B_PCH_SCS_DEV_MEM_SDCMD_CMD_CRC_CHECK_EN BIT3
109 #define B_PCH_SCS_DEV_MEM_NINTSTS_DMA_INTERRUPT BIT3
171 #define B_PCH_PCR_SCS_IOSFCTL_MAX_RD_PEND (BIT3 | BIT2 | BIT1 | BIT0) ///< Max upstream p…

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