| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| H A D | meminit.c | 715 isbM32m(DDRPHY, (DQANAODTPUCTL), (BIT30), (BIT30)); // ODT: Dither PU Enable in ddrphy_init()
716 isbM32m(DDRPHY, (DQANAODTPDCTL), (BIT30), (BIT30)); // ODT: Dither PD Enable in ddrphy_init()
717 isbM32m(DDRPHY, (CLKANAODTPUCTL), (BIT30), (BIT30)); // ODT: Dither PU Enable in ddrphy_init()
718 isbM32m(DDRPHY, (CLKANAODTPDCTL), (BIT30), (BIT30)); // ODT: Dither PD Enable in ddrphy_init()
719 isbM32m(DDRPHY, (DQSANAODTPUCTL), (BIT30), (BIT30)); // ODT: Dither PU Enable in ddrphy_init()
720 isbM32m(DDRPHY, (DQSANAODTPDCTL), (BIT30), (BIT30)); // ODT: Dither PD Enable in ddrphy_init()
731 isbM32m(DDRPHY, (DQANATCOPUCTL), (BIT30), (BIT30)); // TCO: Dither PU Enable in ddrphy_init()
732 isbM32m(DDRPHY, (DQANATCOPDCTL), (BIT30), (BIT30)); // TCO: Dither PD Enable in ddrphy_init()
733 isbM32m(DDRPHY, (CLKANATCOPUCTL), (BIT30), (BIT30)); // TCO: Dither PU Enable in ddrphy_init()
734 isbM32m(DDRPHY, (CLKANATCOPDCTL), (BIT30), (BIT30)); // TCO: Dither PD Enable in ddrphy_init()
[all …]
|
| H A D | general_definitions.h | 41 #undef BIT30
77 #define BIT30 0x40000000U macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/UefiCpuPkg/Include/Register/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/UefiCpuPkg/Include/Register/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/UefiCpuPkg/Include/Register/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/sysutils/edk2/edk2-edk2-stable202102/MdePkg/Include/Register/Intel/ |
| H A D | StmStatusCode.h | 66 #define STM_CRASH_PROTECTION_EXCEPTION (BIT31 | BIT30 | 0xF001)
67 #define STM_CRASH_PROTECTION_EXCEPTION_FAILURE (BIT31 | BIT30 | 0xF002)
68 #define STM_CRASH_DOMAIN_DEGRADATION_FAILURE (BIT31 | BIT30 | 0xF003)
69 #define STM_CRASH_BIOS_PANIC (BIT31 | BIT30 | 0xE000)
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsFia.h | 61 #define B_PCH_PCR_FIA_STRPFUSECFG1_GBE_PCIEPORTSEL (BIT30 | BIT29 | BIT28)
90 #define B_PCH_PCR_FIA_L7O (BIT31 | BIT30 | BIT29 | BIT28)
98 #define B_PCH_PCR_FIA_L15O (BIT31 | BIT30 | BIT29 | BIT28)
106 #define B_PCH_PCR_FIA_L23O (BIT31 | BIT30 | BIT29 | BIT28)
|
| H A D | PchRegsPmc.h | 55 #define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30
107 #define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30
458 #define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power …
496 #define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 P…
519 #define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Dom…
539 #define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qu…
543 #define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qu…
|
| H A D | PchRegsPcie.h | 178 #define B_PCH_PCIE_MPC_HPCE BIT30
306 #define B_PCH_PCIE_PCIECFG2_LBWSSTE BIT30
341 #define B_PCH_PCIE_PCIESTS2_P3PNCCWSSCMES BIT30
409 #define B_PCH_PCIE_FOMS_I (BIT30 | BIT29)
422 #define B_PCH_PCIE_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/ |
| H A D | PchRegsPcie.h | 138 #define B_PCH_PCIE_CFG_MPC_HPCE BIT30
265 #define B_PCH_PCIE_CFG_PCIECFG2_LBWSSTE BIT30
275 #define B_PCH_PCIE_CFG_PCIEDBG_LBWSSTE BIT30
301 #define B_PCH_PCIE_CFG_PCIESTS2_P3PNCCWSSCMES BIT30
327 #define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30
386 #define B_PCH_PCIE_CFG_FOMS_I (BIT30 | BIT29)
399 #define B_PCH_PCIE_CFG_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT29 | BIT28)
|
| H A D | PchRegsFia.h | 66 #define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 | BIT29 | BIT28)
74 #define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 | BIT29 | BIT28)
82 #define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 | BIT29 | BIT28)
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/SimicsIch10Pkg/Include/Register/ |
| H A D | PchRegsPmc.h | 56 #define B_PCH_PMC_GEN_PMCON_A_DC_PP_DIS BIT30
108 #define B_PCH_PMC_BM_CX_CNF_PCIE_BREAK_EN BIT30
459 #define B_PCH_PWRM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power …
497 #define B_PCH_PWRM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 P…
520 #define B_PCH_PWRM_MODPHY_PM_CFG2_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Dom…
540 #define B_PCH_PWRM_CPPM_CG_POLXA_CPPM_GX_QUAL BIT30 ///< CPPM Shutdown Qu…
544 #define B_PCH_PWRM_CPPM_MPG_POL1A_CPPM_MODPHY_QUAL BIT30 ///< CPPM Shutdown Qu…
|
| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| H A D | Lan9118DxeHw.h | 76 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filteri…
261 #define GPIO_LED3_ENABLE BIT30
301 #define MAC_CSR_READ BIT30
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/ArmVirtPkg/Library/FdtPciPcdProducerLib/ |
| H A D | FdtPciPcdProducerLib.c | 33 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
38 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
|