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Searched refs:BIT4 (Results 1 – 25 of 1665) sorted by relevance

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/dports/math/primecount/primecount-7.2/lib/primesieve/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 },
109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 },
112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 },
113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
128 { BIT1, 6, 1, 1 }, { BIT5, 2, 1, 1 }, { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 },
[all …]
H A DEratSmall.cpp115 p[sievingPrime * 6 + 1] &= BIT4; in crossOff()
124 case 1: CHECK_FINISHED(1); *p &= BIT4; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
146 p[sievingPrime * 28 + 10] &= BIT4; in crossOff()
155 case 15: CHECK_FINISHED(15); *p &= BIT4; p += sievingPrime * 2 + 1; in crossOff()
167 p[sievingPrime * 12 + 5] &= BIT4; in crossOff()
176 case 19: CHECK_FINISHED(19); *p &= BIT4; p += sievingPrime * 4 + 2; FALLTHROUGH; in crossOff()
193 p[sievingPrime * 16 + 9] &= BIT4; in crossOff()
214 p[sievingPrime * 0 + 0] &= BIT4; in crossOff()
245 p[sievingPrime * 22 + 17] &= BIT4; in crossOff()
266 p[sievingPrime * 10 + 10] &= BIT4; in crossOff()
[all …]
/dports/math/primesieve/primesieve-7.7/src/
H A DLookupTables.cpp105 { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 },
108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 },
109 { BIT2, 6, 2, 1 }, { BIT7, 4, 2, 1 }, { BIT5, 2, 1, 1 }, { BIT4, 4, 2, 1 },
112 { BIT4, 2, 1, 1 }, { BIT5, 4, 2, 1 }, { BIT7, 6, 4, 1 }, { BIT2, 2, 1, -7 },
113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 },
116 { BIT7, 2, 2, 1 }, { BIT3, 4, 3, 1 }, { BIT4, 6, 5, 1 }, { BIT0, 2, 1, -7 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
128 { BIT1, 6, 1, 1 }, { BIT5, 2, 1, 1 }, { BIT0, 6, 1, 1 }, { BIT4, 4, 1, 1 },
[all …]
H A DEratSmall.cpp115 p[sievingPrime * 6 + 1] &= BIT4; in crossOff()
124 case 1: CHECK_FINISHED(1); *p &= BIT4; p += sievingPrime * 4 + 1; FALLTHROUGH; in crossOff()
146 p[sievingPrime * 28 + 10] &= BIT4; in crossOff()
155 case 15: CHECK_FINISHED(15); *p &= BIT4; p += sievingPrime * 2 + 1; in crossOff()
167 p[sievingPrime * 12 + 5] &= BIT4; in crossOff()
176 case 19: CHECK_FINISHED(19); *p &= BIT4; p += sievingPrime * 4 + 2; FALLTHROUGH; in crossOff()
193 p[sievingPrime * 16 + 9] &= BIT4; in crossOff()
214 p[sievingPrime * 0 + 0] &= BIT4; in crossOff()
245 p[sievingPrime * 22 + 17] &= BIT4; in crossOff()
266 p[sievingPrime * 10 + 10] &= BIT4; in crossOff()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h54 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disabl…
83 …PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x0…
85 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
87 …FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:1…
98 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
107 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
118 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
126 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
161 …{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4…
191 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to…
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h54 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disabl…
83 …PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x0…
85 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
87 …FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:1…
98 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
107 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
118 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
126 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
161 …{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4…
191 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to…
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h54 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disabl…
83 …PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x0…
85 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
87 …FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:1…
98 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
107 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
118 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
126 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
161 …{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4…
191 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to…
[all …]
/dports/mail/spambnc/usr/local/sb/dangerous/aaaworking/
H A Dcidrmatch-procmail.rc75 BIT4=16
85 { BIT4=0 }
185 * $ ${BIT4}^0
198 * $ ${BIT4}^0
212 * $ ${BIT4}^0
227 * $ ${BIT4}^0
303 BIT4=16
313 { BIT4=0 }
410 * $ ${BIT4}^0
528 BIT4=16
[all …]
/dports/mail/spambnc/usr/local/sb/functions/
H A Dcidrmatch.rc80 BIT4=16
90 { BIT4=0 }
190 * $ ${BIT4}^0
203 * $ ${BIT4}^0
217 * $ ${BIT4}^0
232 * $ ${BIT4}^0
308 BIT4=16
318 { BIT4=0 }
415 * $ ${BIT4}^0
533 BIT4=16
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/FetIcc/
H A DeZ_FET_IccMonitor.c96 if(((P6IN & BIT4) == BIT4) && Bios_getTool_id() == eZ_FET_WITH_DCDC in IccMonitor_Process()
97 || ((P6IN & BIT4) == BIT4) && Bios_getTool_id() == eZ_FET_WITH_DCDC_NO_FLOWCTL in IccMonitor_Process()
98 || ((P6IN & BIT4) == BIT4) && Bios_getTool_id() == eZ_FET_WITH_DCDC_V2x)//eZ-FET with DCDC in IccMonitor_Process()
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h97 #define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List
442 #define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW
526 #define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status
562 #define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable
677 #define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap
730 #define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock
797 #define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4)
866 #define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe
896 #define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
933 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h91 #define B_PCH_LPC_DEV_STS_CAP_LIST BIT4 // Capabilities List
436 #define B_PCH_ILB_GNMI_NMIN BIT4 // NMI NOW
520 #define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI BIT4 // PUNIT SCI Status
556 #define B_PCH_SMI_EN_ON_SLP_EN BIT4 // SMI On Sleep Enable
671 #define B_PCH_PMC_PM_CFG_NO_REBOOT BIT4 // No Reboot Strap
724 #define B_PCH_PMC_GEN_PMCON_SMI_LOCK BIT4 // SMI Lock
791 #define B_PCH_PMC_GPI_ROUT_2 (BIT5 | BIT4)
860 #define B_PCH_PMC_PSS_PG_STS_PCIE BIT4 // PCIe
890 #define B_PCH_PMC_D3_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
927 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4 BIT4 // LPSS 0 Function 4
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
375 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
482 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
508 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
529 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
555 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
375 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
482 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
508 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
529 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
555 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
375 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
482 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
508 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
529 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
555 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/
H A DhilFpgaAccess.c63 P1DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
64 P1SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
75 P2DIR |= (BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
76 P2SEL &= ~(BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
87 P3DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
88 P3SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
100 P4SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
111 P5DIR |= (BIT1+BIT2+BIT4+BIT5); // set pins initially to output direction in hil_fpga_init()
114 P5OUT &= ~(BIT2+BIT4); in hil_fpga_init()
137 P9OUT |= BIT0+BIT1+BIT2+BIT4; in hil_fpga_init()
[all …]
H A Darch.h97 (unsigned char)BIT4, // TST, P7.4, (out)
122 (unsigned char)BIT4, // RST, P3.4 (out)
135 (unsigned char)BIT4, // RST
136 (unsigned char)BIT4, // TST
143 (unsigned char)BIT4, // VF2TDI, P5.4 (out)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/
H A DFip006Reg.h66 #define TXF_TFLETS BIT4
75 #define TXE_TFLETE BIT4
84 #define TXC_TFLETC BIT4
93 #define RXF_RFLETS BIT4
102 #define RXE_RFLETE BIT4
111 #define RXC_RFLETC BIT4
118 #define FAULTF_DRCBSFS BIT4
125 #define FAULTC_DRCBSFC BIT4
164 #define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4)
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h30 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
37 #define MSR_CB BIT4 // FDC Busy
92 #define STS0_EC BIT4 // Equipment Check
108 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service w…
123 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from t…
140 #define STS3_T0 BIT4 // Track 0
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h30 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
37 #define MSR_CB BIT4 // FDC Busy
92 #define STS0_EC BIT4 // Equipment Check
108 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service w…
123 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from t…
140 #define STS3_T0 BIT4 // Track 0
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h37 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
44 #define MSR_CB BIT4 // FDC Busy
99 #define STS0_EC BIT4 // Equipment Check
115 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service w…
130 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from t…
147 #define STS3_T0 BIT4 // Track 0
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h30 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
37 #define MSR_CB BIT4 // FDC Busy
92 #define STS0_EC BIT4 // Equipment Check
108 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service w…
123 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from t…
140 #define STS3_T0 BIT4 // Track 0
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Dregisters.h70 cr_i_negative = BIT4(0),
71 cr_i_positive = BIT4(1),
72 cr_i_zero = BIT4(2),
73 cr_i_summary_overflow = BIT4(3),
98 cr_fp_exception = BIT4(0),
99 cr_fp_enabled_exception = BIT4(1),
100 cr_fp_invalid_exception = BIT4(2),
101 cr_fp_overflow_exception = BIT4(3),
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/ppc/
H A Dregisters.h70 cr_i_negative = BIT4(0),
71 cr_i_positive = BIT4(1),
72 cr_i_zero = BIT4(2),
73 cr_i_summary_overflow = BIT4(3),
98 cr_fp_exception = BIT4(0),
99 cr_fp_enabled_exception = BIT4(1),
100 cr_fp_invalid_exception = BIT4(2),
101 cr_fp_overflow_exception = BIT4(3),
/dports/devel/avr-gdb/gdb-7.3.1/sim/ppc/
H A Dregisters.h70 cr_i_negative = BIT4(0),
71 cr_i_positive = BIT4(1),
72 cr_i_zero = BIT4(2),
73 cr_i_summary_overflow = BIT4(3),
98 cr_fp_exception = BIT4(0),
99 cr_fp_enabled_exception = BIT4(1),
100 cr_fp_invalid_exception = BIT4(2),
101 cr_fp_overflow_exception = BIT4(3),

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