Home
last modified time | relevance | path

Searched refs:BIT6 (Results 1 – 25 of 1791) sorted by relevance

12345678910>>...72

/dports/math/primecount/primecount-7.2/lib/primesieve/src/
H A DLookupTables.cpp106 { BIT6, 2, 1, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, -7 },
108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 },
110 { BIT1, 2, 1, 1 }, { BIT0, 4, 1, 1 }, { BIT6, 6, 3, 1 }, { BIT3, 2, 1, -7 },
111 { BIT3, 6, 3, 1 }, { BIT6, 4, 3, 1 }, { BIT0, 2, 1, 1 }, { BIT1, 4, 2, 1 },
113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 },
115 { BIT5, 6, 5, 1 }, { BIT1, 4, 3, 1 }, { BIT2, 2, 1, 1 }, { BIT6, 4, 3, 1 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp118 p[sievingPrime * 16 + 3] &= BIT6; in crossOff()
127 case 4: CHECK_FINISHED(4); *p &= BIT6; p += sievingPrime * 2 + 1; FALLTHROUGH; in crossOff()
144 p[sievingPrime * 18 + 6] &= BIT6; in crossOff()
153 case 13: CHECK_FINISHED(13); *p &= BIT6; p += sievingPrime * 4 + 2; FALLTHROUGH; in crossOff()
170 p[sievingPrime * 22 + 9] &= BIT6; in crossOff()
190 p[sievingPrime * 6 + 3] &= BIT6; in crossOff()
216 p[sievingPrime * 10 + 6] &= BIT6; in crossOff()
242 p[sievingPrime * 12 + 9] &= BIT6; in crossOff()
264 p[sievingPrime * 0 + 0] &= BIT6; in crossOff()
296 p[sievingPrime * 28 + 1] &= BIT6; in crossOff()
[all …]
/dports/math/primesieve/primesieve-7.7/src/
H A DLookupTables.cpp106 { BIT6, 2, 1, 1 }, { BIT2, 4, 1, 1 }, { BIT1, 6, 1, 1 }, { BIT5, 2, 1, -7 },
108 { BIT0, 2, 0, 1 }, { BIT6, 4, 2, 1 }, { BIT2, 6, 2, 1 }, { BIT4, 2, 1, -7 },
110 { BIT1, 2, 1, 1 }, { BIT0, 4, 1, 1 }, { BIT6, 6, 3, 1 }, { BIT3, 2, 1, -7 },
111 { BIT3, 6, 3, 1 }, { BIT6, 4, 3, 1 }, { BIT0, 2, 1, 1 }, { BIT1, 4, 2, 1 },
113 { BIT4, 6, 4, 1 }, { BIT2, 4, 2, 1 }, { BIT6, 2, 2, 1 }, { BIT0, 4, 2, 1 },
115 { BIT5, 6, 5, 1 }, { BIT1, 4, 3, 1 }, { BIT2, 2, 1, 1 }, { BIT6, 4, 3, 1 },
117 { BIT6, 6, 6, 1 }, { BIT5, 4, 4, 1 }, { BIT4, 2, 2, 1 }, { BIT3, 4, 4, 1 },
120 { BIT3, 2, 0, 1 }, { BIT4, 4, 0, 1 }, { BIT5, 6, 0, 1 }, { BIT6, 2, 0, -7 }
125 { BIT0, 10, 2, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 2, 1, 1 },
127 { BIT4, 4, 1, 1 }, { BIT3, 2, 0, 1 }, { BIT7, 4, 1, 1 }, { BIT6, 6, 2, 1 },
[all …]
H A DEratSmall.cpp118 p[sievingPrime * 16 + 3] &= BIT6; in crossOff()
127 case 4: CHECK_FINISHED(4); *p &= BIT6; p += sievingPrime * 2 + 1; FALLTHROUGH; in crossOff()
144 p[sievingPrime * 18 + 6] &= BIT6; in crossOff()
153 case 13: CHECK_FINISHED(13); *p &= BIT6; p += sievingPrime * 4 + 2; FALLTHROUGH; in crossOff()
170 p[sievingPrime * 22 + 9] &= BIT6; in crossOff()
190 p[sievingPrime * 6 + 3] &= BIT6; in crossOff()
216 p[sievingPrime * 10 + 6] &= BIT6; in crossOff()
242 p[sievingPrime * 12 + 9] &= BIT6; in crossOff()
264 p[sievingPrime * 0 + 0] &= BIT6; in crossOff()
296 p[sievingPrime * 28 + 1] &= BIT6; in crossOff()
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/uart/
H A DFetCom.h50 #define uart_RtsIn() {P2DIR &=~ BIT6;} // RTS input
55 #define uart_RtsRen() {P2REN |= BIT6;} // RTS resistor
60 #define com_RtsIe() {P2IE |= BIT6;} // RTS Interrupt enable
61 #define com_RtsInterruptDisable() {P2IE &= ~BIT6;} // RTS Interrupt disable
65 #define uart_RtsStatus() ((P2IN & BIT6)==BIT6)
96 #define RTS_PULLDOWN_BIT ( BIT6 )
97 #define rtsSetPullDownDir() (P2DIR &= ~BIT6)
99 #define rtsClearPullDownDir() (P2DIR &= ~BIT6)
102 #define RTS_PULLUP_BIT ( BIT6 )
103 #define rtsSetPullUpDir() (P2DIR &= ~BIT6)
[all …]
/dports/mail/spambnc/usr/local/sb/dangerous/aaaworking/
H A Dcidrmatch-procmail.rc39 BIT6=64
49 { BIT6=0 }
159 * $ ${BIT6}^0
170 * $ ${BIT6}^0
183 * $ ${BIT6}^0
196 * $ ${BIT6}^0
210 * $ ${BIT6}^0
267 BIT6=64
277 { BIT6=0 }
492 BIT6=64
[all …]
/dports/mail/spambnc/usr/local/sb/functions/
H A Dcidrmatch.rc44 BIT6=64
54 { BIT6=0 }
164 * $ ${BIT6}^0
175 * $ ${BIT6}^0
188 * $ ${BIT6}^0
201 * $ ${BIT6}^0
215 * $ ${BIT6}^0
272 BIT6=64
282 { BIT6=0 }
497 BIT6=64
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/EnergyTrace_TSPA/
H A DVCC_Current.c355 P2OUT &= ~(BIT6+BIT7); in calibrationSetLoad()
358 if (i2cData & BIT0) { P2DIR |= BIT6; } in calibrationSetLoad()
359 else { P2DIR &= ~BIT6; } in calibrationSetLoad()
375 P2DIR |= BIT6+BIT7; in calibrationSetLoad()
378 if (i2cData & BIT0) { P2OUT |= BIT6; } in calibrationSetLoad()
379 else { P2OUT &= ~BIT6; } in calibrationSetLoad()
484 P2SEL &= ~(BIT6+BIT7); // XT1 pins to GPIO functionality in main()
485 P2SEL2 &= ~(BIT6+BIT7); in main()
487 P2DIR = BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7; in main()
510 P2SEL2 &= ~(BIT6+BIT7); in main()
[all …]
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h79 #define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable
204 #define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable
428 #define B_PCH_ILB_DEF1_ECWS BIT6 // 8254 Early CW Select
438 #define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable
798 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
864 #define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio
894 #define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
931 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
1025 #define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status
1105 #define B_PCH_RTC_REGISTERD_RESERVED BIT6
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
H A DPchRegsPcu.h73 #define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable
198 #define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable
422 #define B_PCH_ILB_DEF1_ECWS BIT6 // 8254 Early CW Select
432 #define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable
792 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
858 #define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio
888 #define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
925 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
1019 #define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status
1099 #define B_PCH_RTC_REGISTERD_RESERVED BIT6
[all …]
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/
H A DPcieRegs.h37 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
44 #define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable…
49 #define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
66 #define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
82 #define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
85 #define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsLpc.h54 #define B_LPC_CFG_SERIRQ_CNT_SIRQMD BIT6
73 #define B_LPC_CFG_IOD_COMB (BIT6 | BIT5 |BIT4)
118 #define B_LPC_CFG_ULKMC_PSTATE BIT6
157 #define B_LPC_CFG_BDE_LEG_E BIT6
170 #define B_LPC_CFG_FVEC0_SATA_PORT23_CAP BIT6
197 #define B_LPC_CFG_BC_BBS BIT6 ///< Boot BIOS strap
230 #define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6
282 #define B_RTC_PCR_CONF_HPM_HW_DIS BIT6 ///< RTC High Power Mode HW Disa…
341 #define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
H A DPchRegsPcie.h119 #define B_PCH_PCIE_CFG_CCFG_UNRS (BIT6 | BIT5 | BIT4)
125 #define B_PCH_PCIE_CFG_MPC2_LSTP BIT6
166 #define B_PCH_PCIE_CFG_RPDCGEN_PTOCGE BIT6
186 #define B_PCH_PCIE_CFG_PHYCTL2_TDFT (BIT7 | BIT6)
193 #define B_PCH_PCIE_CFG_IOSFSBCS_SCPTCGE BIT6
208 #define B_PCH_PCIE_CFG_STRPFUSECFG_ASPMDIS BIT6
226 #define B_PCH_PCIE_CFG_EX_CES_BT BIT6 ///< Bad TLP Status
251 #define B_PCH_PCIE_CFG_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
335 #define B_PCH_PCIE_CFG_PCIEPMECTL2_L23RDYSCPGE BIT6
451 #define B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number
[all …]
H A DPchRegsSata.h111 #define B_SATA_CFG_PC_AUX_CUR (BIT8 | BIT7 | BIT6)
157 #define B_SATA_CFG_MAP_PORT6_PCD BIT6
174 #define B_SATA_CFG_PCS_P6E BIT6
187 #define B_SATA_CFG_SATAGC_AIES BIT6
266 #define B_SATA_CFG_BFCS_BIST_FIS_A BIT6
324 #define B_SATA_MEM_AHCI_CAP_EMS BIT6
336 #define B_SATA_MEM_AHCI_IS_PORT6 BIT6
346 #define B_SATA_MEM_PORT6_IMPLEMENTED BIT6
384 #define B_SATA_MEM_AHCI_SFM_HDDLK BIT6
446 #define B_SATA_MEM_AHCI_PXIS_PCS BIT6
[all …]
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/fw/fet/FetInit/
H A DeZ_FET_init.c57 P5SEL = (BIT0+BIT6); in init_BiosPorts()
66 P6OUT &= ~(BIT6); // set Reset to 1 -> drive device reset in init_BiosPorts()
68 P6OUT = (BIT6); // release Reset start Sub MCU in init_BiosPorts()
69 P2REN |= BIT6; // enable pull down for RTS uart line in init_BiosPorts()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/
H A DFip006Reg.h64 #define TXF_TSSRS BIT6
73 #define TXE_TSSRE BIT6
82 #define TXC_TSSRC BIT6
91 #define RXF_RSSRS BIT6
100 #define RXE_RSSRE BIT6
109 #define RXC_RSSRC BIT6
164 #define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4)
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Include/
H A DPcieRegs.h69 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
76 #define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable…
81 #define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
115 #define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
142 #define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
152 #define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
184 #define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -…
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Include/
H A DPcieRegs.h69 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
77 #define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable…
82 #define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
116 #define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
143 #define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
153 #define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
185 #define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -…
/dports/devel/msp430-debug-stack/msp430-debug-stack-3.15.0.1/Bios/src/hil/msp_fet/
H A DhilFpgaAccess.c63 P1DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
64 P1SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
75 P2DIR |= (BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins to output direction in hil_fpga_init()
76 P2SEL &= ~(BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
87 P3DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
88 P3SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
99 P4DIR |= (BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); // set pins initially to output direction in hil_fpga_init()
100 P4SEL &= ~(BIT0+BIT1+BIT2+BIT3+BIT4+BIT5+BIT6+BIT7); in hil_fpga_init()
112 P5DIR &= ~(BIT6); in hil_fpga_init()
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h39 #define MSR_DIO BIT6 // Data Input/Output
74 #define CMD_MFM BIT6
90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
121 #define STS2_CM BIT6 // Control Mark
136 #define STS3_WP BIT6 // Write Protected
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h39 #define MSR_DIO BIT6 // Data Input/Output
74 #define CMD_MFM BIT6
90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
121 #define STS2_CM BIT6 // Control Mark
136 #define STS3_WP BIT6 // Write Protected
/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h46 #define MSR_DIO BIT6 // Data Input/Output
81 #define CMD_MFM BIT6
97 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
128 #define STS2_CM BIT6 // Control Mark
143 #define STS3_WP BIT6 // Write Protected
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
H A DFdc.h39 #define MSR_DIO BIT6 // Data Input/Output
74 #define CMD_MFM BIT6
90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code
121 #define STS2_CM BIT6 // Control Mark
136 #define STS3_WP BIT6 // Write Protected
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsPcie.h165 #define B_PCH_PCIE_MPC2_LSTP BIT6
206 #define B_PCH_PCIE_RPDCGEN_PTOCGE BIT6
226 #define B_PCH_PCIE_PHYCTL2_TDFT (BIT7 | BIT6)
233 #define B_PCH_PCIE_IOSFSBCS_SCPTCGE BIT6
248 #define B_PCH_PCIE_STRPFUSECFG_ASPMDIS BIT6
266 #define B_PCH_PCIE_EX_CES_BT BIT6 ///< Bad TLP Status
292 #define B_PCH_PCIE_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
358 #define B_PCH_PCIE_PCIEPMECTL2_L23RDYSCPGE BIT6
484 #define B_PCH_PCR_SPX_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Numb…
503 #define B_PCH_PCR_SPX_PCIEHBP_PCIELDO BIT6 ///< PCIe link down overr…
H A DPchRegsSata.h140 #define B_PCH_LP_SATA_MAP_SMS_MASK BIT6
176 #define B_PCH_H_SATA_MAP_PORT6_PCD BIT6
194 #define B_PCH_H_SATA_PCS_P6E BIT6
208 #define B_PCH_SATA_SATAGC_AIES BIT6
287 #define B_PCH_SATA_BFCS_BIST_FIS_A BIT6
346 #define B_PCH_SATA_AHCI_CAP_EMS BIT6
358 #define B_PCH_SATA_AHCI_IS_PORT6 BIT6
369 #define B_PCH_SATA_PORT6_IMPLEMENTED BIT6
408 #define B_PCH_SATA_AHCI_RSTF_HDDLK BIT6
470 #define B_PCH_SATA_AHCI_PXIS_PCS BIT6
[all …]

12345678910>>...72