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Searched refs:CFA_REG (Results 1 – 25 of 90) sorted by relevance

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/dports/lang/gcc12-devel/gcc-12-20211205/gcc/ada/
H A Dsigtramp-vxworks-target.h205 #define CFA_REG 15 macro
210 #define CFA_REG 19 macro
213 #define CFA_REG 8 macro
218 #define CFA_REG 7 macro
223 #define CFA_REG 15 macro
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/devel/android-tools-fastboot/platform_system_core-platform-tools-29.0.5/libunwindstack/tests/
H A DDwarfCfaTest.cpp524 ASSERT_EQ(5U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
525 ASSERT_EQ(100U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
539 ASSERT_EQ(0x7fU, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
540 ASSERT_EQ(0x74U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
568 ASSERT_EQ(0x30U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
612 ASSERT_EQ(20U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
627 ASSERT_EQ(60U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
654 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
669 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
696 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
[all …]
H A DDwarfSectionImplTest.cpp206 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {20, 0}}; in TYPED_TEST_P()
212 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
213 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_INVALID, {0, 0}}; in TYPED_TEST_P()
218 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
219 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_OFFSET, {0, 0}}; in TYPED_TEST_P()
224 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
239 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {9, 0}}; in TYPED_TEST_P()
257 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {6, 0}}; in TYPED_TEST_P()
275 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {8, 0}}; in TYPED_TEST_P()
300 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {8, 0}}; in TYPED_TEST_P()
[all …]
/dports/devel/android-tools-adb/platform_system_core-android-9.0.0_r3/libunwindstack/tests/
H A DDwarfCfaTest.cpp524 ASSERT_EQ(5U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
525 ASSERT_EQ(100U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
539 ASSERT_EQ(0x7fU, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
540 ASSERT_EQ(0x74U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
568 ASSERT_EQ(0x30U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
612 ASSERT_EQ(20U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
627 ASSERT_EQ(60U, loc_regs[CFA_REG].values[1]); in TYPED_TEST_P()
654 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
669 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
696 ASSERT_EQ(3U, loc_regs[CFA_REG].values[0]); in TYPED_TEST_P()
[all …]
H A DDwarfSectionImplTest.cpp202 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {20, 0}}; in TYPED_TEST_P()
208 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
209 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_INVALID, {0, 0}}; in TYPED_TEST_P()
214 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
215 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_OFFSET, {0, 0}}; in TYPED_TEST_P()
220 loc_regs.erase(CFA_REG); in TYPED_TEST_P()
235 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {9, 0}}; in TYPED_TEST_P()
253 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {6, 0}}; in TYPED_TEST_P()
271 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {8, 0}}; in TYPED_TEST_P()
296 loc_regs[CFA_REG] = DwarfLocation{DWARF_LOCATION_REGISTER, {8, 0}}; in TYPED_TEST_P()
[all …]
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/ada/
H A Dsigtramp-armvxw.c160 #define CFA_REG 8 macro
163 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
201 TCR("stmfd sp!, {r"S(CFA_REG)", fp, ip, lr, pc}") \
203 TCR("ldr r"S(CFA_REG)", [ip]") \
210 TCR("ldmfd sp, {r"S(CFA_REG)", fp, sp, pc}")
H A Dsigtramp-ppcvxw.c166 #define CFA_REG 15 macro
169 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
238 TCR("stw %r" S(CFA_REG) ",8(%r1)") \
241 TCR("mr %r" S(CFA_REG) ", %r7") \
249 TCR("lwz %r" S(CFA_REG) ",8(%r1)") \
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
H A Dsigtramp-ios.c110 #define CFA_REG 19 macro
130 TCR(".cfi_def_cfa " S(CFA_REG) ", 0")
188 TCR("stp x" S(CFA_REG) ", x" S(BASE_REG) ", [sp, #16]") \
191 TCR("ldr x" S(CFA_REG) ", [x2, #" S(REG_OFFSET_GR(31)) "]") \
197 TCR("ldp x" S(CFA_REG) ", x" S(BASE_REG)" , [sp, #16]") \
/dports/lang/gcc9/gcc-9.4.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/devel/avr-gcc/gcc-10.2.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc10/gcc-10.3.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc204 #define CFA_REG 15
209 #define CFA_REG 19
212 #define CFA_REG 8
217 #define CFA_REG 7
222 #define CFA_REG 15
229 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
304 TCR("mr %r" S(CFA_REG) ", %r7") \
334 TCR("mr %r" S(CFA_REG) ", %r7") \
343 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
423 TCR("mov x" S(CFA_REG) ", x2") \
[all …]
/dports/lang/gcc11/gcc-11.2.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/ada/
H A Dsigtramp-vxworks-target.inc205 #define CFA_REG 15
210 #define CFA_REG 19
213 #define CFA_REG 8
218 #define CFA_REG 7
223 #define CFA_REG 15
230 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
305 TCR("mr %r" S(CFA_REG) ", %r7") \
335 TCR("mr %r" S(CFA_REG) ", %r7") \
344 TCR("ld %r" S(CFA_REG) ",8(%r1)") \
427 TCR("mov x" S(CFA_REG) ", x4") \
[all …]
/dports/lang/gcc48/gcc-4.8.5/gcc/ada/
H A Dsigtramp-ppcvxw.c165 #define CFA_REG 15 macro
168 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
236 TCR("stw %r" S(CFA_REG) ",8(%r1)") \
239 TCR("mr %r" S(CFA_REG) ", %r7") \
247 TCR("lwz %r" S(CFA_REG) ",8(%r1)") \
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/ada/
H A Dsigtramp-ppcvxw.c165 #define CFA_REG 15 macro
168 CR(".cfi_def_cfa " S(CFA_REG) ", 0")
236 TCR("stw %r" S(CFA_REG) ",8(%r1)") \
239 TCR("mr %r" S(CFA_REG) ", %r7") \
247 TCR("lwz %r" S(CFA_REG) ",8(%r1)") \

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