| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 55 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
290 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
293 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 55 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
290 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
293 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 55 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
290 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
293 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 55 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
290 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
293 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 55 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
290 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
293 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1) macro
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); in cadence_qspi_apb_set_clk_mode()
296 reg |= CQSPI_REG_CONFIG_CLK_POL; in cadence_qspi_apb_set_clk_mode()
|