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Searched refs:D32_MASK (Results 1 – 19 of 19) sorted by relevance

/dports/emulators/simh-hp3000/simh-hp3000-3.11.0.10/SCP/HP3000/
H A Dhp3000_defs.h399 #define D32_MASK 037777777777u /* 32-bit data mask */ macro
568 #define NEG32(x) ((~(x) + 1) & D32_MASK)
620 #define UPPER_DWORD(q) (uint32) ((q) >> D32_WIDTH & D32_MASK)
621 #define LOWER_DWORD(q) (uint32) ((q) & D32_MASK)
H A Dhp3000_sys.c622 { "CMPT", TO_DWORD (0000006, 0020477), opB31, D32_MASK },
623 { "TCCS", TO_DWORD (0000010, 0020477), opCC7, D32_MASK },
624 { "CVND", TO_DWORD (0000020, 0020477), opSCS4, D32_MASK },
625 { "LDW", TO_DWORD (0000040, 0020477), opS31, D32_MASK },
626 { "LDDW", TO_DWORD (0000042, 0020477), opS31, D32_MASK },
627 { "TR", TO_DWORD (0000044, 0020477), opB31, D32_MASK },
628 { "ABSD", TO_DWORD (0000046, 0020477), opS31, D32_MASK },
629 { "NEGD", TO_DWORD (0000050, 0020477), opS31, D32_MASK },
2351 …bitmask = D32_MASK; /* to prevent shifting the bit off the MSB e… in fmt_bitset()
H A Dhp3000_cpu_base.c1966 return (uint32) sum & D32_MASK; /* return the lower 32 bits of the sum */ in add_32()
1998 return (uint32) difference & D32_MASK; /* return the lower 32 bits of the diff… in sub_32()
2066 { D32_SIGN, D32_MASK & ~D32_SIGN, D32_WIDTH } /* 32-bit operand properties */ in shift_16_32()
/dports/emulators/simh-hpdoc/simh-hpdoc-3.11.0/SCP/HP3000/
H A Dhp3000_cpu_fp.c688 al = (uint32) (multiplicand.mantissa & D32_MASK); /* into high and low double-words */ in multiply()
691 bl = (uint32) (multiplier.mantissa & D32_MASK); /* into high and low double-words */ in multiply()
698 …carry = ((ll >> D32_WIDTH) + (hl & D32_MASK) /* add the upper half of "ll" to the lower hal… in multiply()
699 … + (lh & D32_MASK)) >> D32_WIDTH; /* and "lh" and shift to leave just the carry bit */ in multiply()
800 bl = divisor.mantissa & D32_MASK; /* into high and low halves */ in divide()
H A Dhp3000_sys.c624 { "CMPT", TO_DWORD (0000006, 0020477), opB31, D32_MASK },
625 { "TCCS", TO_DWORD (0000010, 0020477), opCC7, D32_MASK },
626 { "CVND", TO_DWORD (0000020, 0020477), opSCS4, D32_MASK },
627 { "LDW", TO_DWORD (0000040, 0020477), opS31, D32_MASK },
628 { "LDDW", TO_DWORD (0000042, 0020477), opS31, D32_MASK },
629 { "TR", TO_DWORD (0000044, 0020477), opB31, D32_MASK },
630 { "ABSD", TO_DWORD (0000046, 0020477), opS31, D32_MASK },
631 { "NEGD", TO_DWORD (0000050, 0020477), opS31, D32_MASK },
2334 …bitmask = D32_MASK; /* to prevent shifting the bit off the MSB e… in fmt_bitset()
H A Dhp3000_defs.h411 #define D32_MASK 037777777777u /* 32-bit data mask */ macro
576 #define NEG32(x) ((~(x) + 1) & D32_MASK)
H A Dhp3000_cpu_base.c1963 return (uint32) sum & D32_MASK; /* return the lower 32 bits of the sum */ in add_32()
1995 return (uint32) difference & D32_MASK; /* return the lower 32 bits of the diff… in sub_32()
2063 { D32_SIGN, D32_MASK & ~D32_SIGN, D32_WIDTH } /* 32-bit operand properties */ in shift_16_32()
/dports/emulators/simh-hpdoc/simh-hpdoc-3.11.0/SCP/HP2100/
H A Dhp2100_cpu_fp.c131 (((uint32) D32_MASK) << (32 - (s))): 0)) & D32_MASK
133 #define FR_NEG(v) ((~(v) + 1) & D32_MASK)
245 res.fr = (t4 + t5) & D32_MASK; /* bit<0> is lost */ in f_mul()
H A Dhp2100_sys.c1556 { "VADD", TO_DWORD (0000000u, 0101460u), opMA7I, D32_MASK },
1557 { "VSUB", TO_DWORD (0000020u, 0101460u), opMA7I, D32_MASK },
1558 { "VMPY", TO_DWORD (0000040u, 0101460u), opMA7I, D32_MASK },
1559 { "VDIV", TO_DWORD (0000060u, 0101460u), opMA7I, D32_MASK },
1560 { "VSAD", TO_DWORD (0000400u, 0101460u), opMA6I, D32_MASK },
1561 { "VSSB", TO_DWORD (0000420u, 0101460u), opMA6I, D32_MASK },
1562 { "VSMY", TO_DWORD (0000440u, 0101460u), opMA6I, D32_MASK },
1563 { "VSDV", TO_DWORD (0000460u, 0101460u), opMA6I, D32_MASK },
1566 { "DVADD", TO_DWORD (0004002u, 0105460u), opMA7I, D32_MASK },
1567 { "DVSUB", TO_DWORD (0004022u, 0105460u), opMA7I, D32_MASK },
[all …]
H A Dhp2100_defs.h470 #define D32_MASK 037777777777u /* 32-bit data mask */ macro
652 #define NEG32(x) ((~(x) + 1) & D32_MASK)
H A Dhp2100_cpu_fpp.c495 packed.dword = (uint32) (unpacked >> 32) & D32_MASK; /* pack double integer */ in pack_int()
861 al = (uint32) (multiplicand.mantissa & D32_MASK); /* into high and low parts */ in multiply()
863 bl = (uint32) (multiplier.mantissa & D32_MASK); /* into high and low parts */ in multiply()
974 bl = divisor.mantissa & D32_MASK; /* into high and low parts */ in divide()
H A Dhp2100_cpu1.c208 …O = (~operand & mask & D32_MASK) != 0; /* then set overflow if any of the lost bits are zeros */ in cpu_eau()
210 … O = (operand & mask & D32_MASK) != 0; /* so set overflow if any of the lost bits are ones */ in cpu_eau()
H A Dhp2100_cpu3.c707 t = (uint32) (t64 & D32_MASK); /* else lower 32 bits of result */ in cpu_dbi()
/dports/emulators/simh-hp2100/simh-hp2100-3.11.0.31/SCP/HP2100/
H A Dhp2100_cpu_fp.c131 (((uint32) D32_MASK) << (32 - (s))): 0)) & D32_MASK
133 #define FR_NEG(v) ((~(v) + 1) & D32_MASK)
245 res.fr = (t4 + t5) & D32_MASK; /* bit<0> is lost */ in f_mul()
H A Dhp2100_sys.c1556 { "VADD", TO_DWORD (0000000u, 0101460u), opMA7I, D32_MASK },
1557 { "VSUB", TO_DWORD (0000020u, 0101460u), opMA7I, D32_MASK },
1558 { "VMPY", TO_DWORD (0000040u, 0101460u), opMA7I, D32_MASK },
1559 { "VDIV", TO_DWORD (0000060u, 0101460u), opMA7I, D32_MASK },
1560 { "VSAD", TO_DWORD (0000400u, 0101460u), opMA6I, D32_MASK },
1561 { "VSSB", TO_DWORD (0000420u, 0101460u), opMA6I, D32_MASK },
1562 { "VSMY", TO_DWORD (0000440u, 0101460u), opMA6I, D32_MASK },
1563 { "VSDV", TO_DWORD (0000460u, 0101460u), opMA6I, D32_MASK },
1566 { "DVADD", TO_DWORD (0004002u, 0105460u), opMA7I, D32_MASK },
1567 { "DVSUB", TO_DWORD (0004022u, 0105460u), opMA7I, D32_MASK },
[all …]
H A Dhp2100_defs.h493 #define D32_MASK 037777777777u /* 32-bit data mask */ macro
675 #define NEG32(x) ((~(x) + 1) & D32_MASK)
H A Dhp2100_cpu_fpp.c495 packed.dword = (uint32) (unpacked >> 32) & D32_MASK; /* pack double integer */ in pack_int()
861 al = (uint32) (multiplicand.mantissa & D32_MASK); /* into high and low parts */ in multiply()
863 bl = (uint32) (multiplier.mantissa & D32_MASK); /* into high and low parts */ in multiply()
974 bl = divisor.mantissa & D32_MASK; /* into high and low parts */ in divide()
H A Dhp2100_cpu1.c208 …O = (~operand & mask & D32_MASK) != 0; /* then set overflow if any of the lost bits are zeros */ in cpu_eau()
210 … O = (operand & mask & D32_MASK) != 0; /* so set overflow if any of the lost bits are ones */ in cpu_eau()
H A Dhp2100_cpu3.c707 t = (uint32) (t64 & D32_MASK); /* else lower 32 bits of result */ in cpu_dbi()