/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 in lowlevel_init() 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK) in lowlevel_init()
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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/mach-ath79/qca956x/ |
H A D | ddr.c | 94 #define DDR_CONFIG_TRAS_LSB 0 macro 97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
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