1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
4 *
5 * Based on QSDK
6 */
7
8 #include <common.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/addrspace.h>
12 #include <asm/types.h>
13 #include <linux/delay.h>
14 #include <mach/ar71xx_regs.h>
15 #include <mach/ath79.h>
16
17 #define DDR_FSM_WAIT_CTRL_VAL 0xa12
18 #define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30
19 #define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000
20 #define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) \
21 (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
22 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20
23 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000
24 #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) \
25 (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
26 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19
27 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000
28 #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) \
29 (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
30 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18
31 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000
32 #define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) \
33 (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
34 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17
35 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000
36 #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) \
37 (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
38 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16
39 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000
40 #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) \
41 (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
42 #define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB 15
43 #define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK 0x00008000
44 #define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(x) \
45 (((x) << DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK)
46 #define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB 14
47 #define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK 0x00004000
48 #define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(x) \
49 (((x) << DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK)
50 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6
51 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040
52 #define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) \
53 (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
54 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2
55 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004
56 #define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) \
57 (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
58 #define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1
59 #define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002
60 #define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) \
61 (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
62 #define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31
63 #define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000
64 #define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) \
65 (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
66 #define DDR_CONFIG_OPEN_PAGE_LSB 30
67 #define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000
68 #define DDR_CONFIG_OPEN_PAGE_SET(x) \
69 (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
70 #define DDR_CONFIG_CAS_LATENCY_LSB 27
71 #define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000
72 #define DDR_CONFIG_CAS_LATENCY_SET(x) \
73 (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
74 #define DDR_CONFIG_TMRD_LSB 23
75 #define DDR_CONFIG_TMRD_MASK 0x07800000
76 #define DDR_CONFIG_TMRD_SET(x) \
77 (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
78 #define DDR_CONFIG_TRFC_LSB 17
79 #define DDR_CONFIG_TRFC_MASK 0x007e0000
80 #define DDR_CONFIG_TRFC_SET(x) \
81 (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
82 #define DDR_CONFIG_TRRD_LSB 13
83 #define DDR_CONFIG_TRRD_MASK 0x0001e000
84 #define DDR_CONFIG_TRRD_SET(x) \
85 (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
86 #define DDR_CONFIG_TRP_LSB 9
87 #define DDR_CONFIG_TRP_MASK 0x00001e00
88 #define DDR_CONFIG_TRP_SET(x) \
89 (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
90 #define DDR_CONFIG_TRCD_LSB 5
91 #define DDR_CONFIG_TRCD_MASK 0x000001e0
92 #define DDR_CONFIG_TRCD_SET(x) \
93 (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
94 #define DDR_CONFIG_TRAS_LSB 0
95 #define DDR_CONFIG_TRAS_MASK 0x0000001f
96 #define DDR_CONFIG_TRAS_SET(x) \
97 (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
98 #define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31
99 #define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000
100 #define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) \
101 (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
102 #define DDR_CONFIG2_SWAP_A26_A27_LSB 30
103 #define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000
104 #define DDR_CONFIG2_SWAP_A26_A27_SET(x) \
105 (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
106 #define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26
107 #define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000
108 #define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) \
109 (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
110 #define DDR_CONFIG2_TWTR_LSB 21
111 #define DDR_CONFIG2_TWTR_MASK 0x03e00000
112 #define DDR_CONFIG2_TWTR_SET(x) \
113 (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
114 #define DDR_CONFIG2_TRTP_LSB 17
115 #define DDR_CONFIG2_TRTP_MASK 0x001e0000
116 #define DDR_CONFIG2_TRTP_SET(x) \
117 (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
118 #define DDR_CONFIG2_TRTW_LSB 12
119 #define DDR_CONFIG2_TRTW_MASK 0x0001f000
120 #define DDR_CONFIG2_TRTW_SET(x) \
121 (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
122 #define DDR_CONFIG2_TWR_LSB 8
123 #define DDR_CONFIG2_TWR_MASK 0x00000f00
124 #define DDR_CONFIG2_TWR_SET(x) \
125 (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
126 #define DDR_CONFIG2_CKE_LSB 7
127 #define DDR_CONFIG2_CKE_MASK 0x00000080
128 #define DDR_CONFIG2_CKE_SET(x) \
129 (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
130 #define DDR_CONFIG2_CNTL_OE_EN_LSB 5
131 #define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020
132 #define DDR_CONFIG2_CNTL_OE_EN_SET(x) \
133 (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
134 #define DDR_CONFIG2_BURST_LENGTH_LSB 0
135 #define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f
136 #define DDR_CONFIG2_BURST_LENGTH_SET(x) \
137 (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
138 #define RST_BOOTSTRAP_ADDRESS 0x180600b0
139 #define PMU2_SWREGMSB_LSB 22
140 #define PMU2_SWREGMSB_MASK 0xffc00000
141 #define PMU2_SWREGMSB_SET(x) \
142 (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
143 #define PMU2_PGM_LSB 21
144 #define PMU2_PGM_MASK 0x00200000
145 #define PMU2_PGM_SET(x) \
146 (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
147
148 #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)
149
150 /*
151 * DDR2 DDR1
152 * 0x40c3 25MHz 0x4186 25Mhz
153 * 0x4138 40MHz 0x4270 40Mhz
154 */
155 #define CFG_DDR2_REFRESH_VAL 0x40c3
156 #define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \
157 DDR_CONFIG_OPEN_PAGE_SET(0x1) | DDR_CONFIG_CAS_LATENCY_SET(0x4) | \
158 DDR_CONFIG_TMRD_SET(0x6) | DDR_CONFIG_TRFC_SET(0x16) | \
159 DDR_CONFIG_TRRD_SET(0x7) | DDR_CONFIG_TRP_SET(0xb) | \
160 DDR_CONFIG_TRCD_SET(0xb) | DDR_CONFIG_TRAS_SET(0)
161 #define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \
162 DDR_CONFIG2_SWAP_A26_A27_SET(0x0) | DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xa) | \
163 DDR_CONFIG2_TWTR_SET(0x16) | DDR_CONFIG2_TRTP_SET(0xa) | \
164 DDR_CONFIG2_TRTW_SET(0xe) | DDR_CONFIG2_TWR_SET(0x2) | \
165 DDR_CONFIG2_CKE_SET(0x1) | DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \
166 DDR_CONFIG2_BURST_LENGTH_SET(0x8)
167
168 #define CFG_DDR2_CONFIG3_VAL 0x0000000e
169 #define CFG_DDR2_EXT_MODE_VAL1 0x782
170 #define CFG_DDR2_EXT_MODE_VAL2 0x402
171 #define CFG_DDR2_MODE_VAL_INIT 0xb53
172 #define CFG_DDR2_MODE_VAL 0xa53
173 #define CFG_DDR2_TAP_VAL 0x10
174 #define CFG_DDR2_EN_TWL_VAL 0x00001e91
175 #define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff
176
177 #define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \
178 DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \
179 DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \
180 DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \
181 DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \
182 DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1) | \
183 DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \
184 DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1)
185
186 DECLARE_GLOBAL_DATA_PTR;
187
qca956x_ddr_init(void)188 void qca956x_ddr_init(void)
189 {
190 u32 ddr_config, ddr_config2, ddr_config3, mod_val, \
191 mod_val_init, cycle_val, tap_val, ctl_config;
192 void __iomem *ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
193 MAP_NOCACHE);
194 void __iomem *srif_regs = map_physmem(QCA956X_SRIF_BASE, QCA956X_SRIF_SIZE,
195 MAP_NOCACHE);
196
197 ddr_config = CFG_DDR2_CONFIG_VAL;
198 ddr_config2 = CFG_DDR2_CONFIG2_VAL;
199 ddr_config3 = CFG_DDR2_CONFIG3_VAL;
200 mod_val_init = CFG_DDR2_MODE_VAL_INIT;
201 mod_val = CFG_DDR2_MODE_VAL;
202 tap_val = CFG_DDR2_TAP_VAL;
203 cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16;
204 ctl_config = CFG_DDR_CTL_CONFIG | DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) |
205 DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1) | CPU_DDR_SYNC_MODE;
206
207 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
208 udelay(10);
209
210 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
211 udelay(10);
212
213 writel(ctl_config, ddr_regs + QCA956X_DDR_REG_CTL_CONF);
214 udelay(10);
215
216 writel(cycle_val, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
217 udelay(100);
218
219 writel(0x74444444, ddr_regs + QCA956X_DDR_REG_BURST);
220 udelay(100);
221
222 writel(0x44444444, ddr_regs + QCA956X_DDR_REG_BURST2);
223 udelay(100);
224
225 writel(DDR_FSM_WAIT_CTRL_VAL, ddr_regs + QCA956X_DDR_REG_FSM_WAIT_CTRL);
226 udelay(100);
227
228 writel(0xfffff, ddr_regs + QCA956X_DDR_REG_TIMEOUT_MAX);
229 udelay(100);
230
231 writel(ddr_config, ddr_regs + AR71XX_DDR_REG_CONFIG);
232 udelay(100);
233
234 writel(ddr_config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
235 udelay(100);
236
237 writel(ddr_config3, ddr_regs + QCA956X_DDR_REG_DDR3_CONFIG);
238 udelay(100);
239
240 writel(CFG_DDR2_EN_TWL_VAL, ddr_regs + QCA956X_DDR_REG_DDR2_CONFIG);
241 udelay(100);
242
243 writel(ddr_config2 | 0x80, ddr_regs + AR71XX_DDR_REG_CONFIG2); /* CKE Enable */
244 udelay(100);
245
246 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */
247 udelay(10);
248
249 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR2);
250 writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR2 */
251 udelay(10);
252
253 writel(0, ddr_regs + QCA956X_DDR_REG_DDR2_EMR3);
254 writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR3 */
255 udelay(10);
256
257 /* EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled */
258 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);
259 udelay(100);
260
261 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
262 udelay(10);
263
264 writel(mod_val_init, ddr_regs + AR71XX_DDR_REG_MODE);
265 udelay(1000);
266
267 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR Write */
268 udelay(10);
269
270 writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Precharge */
271 udelay(10);
272
273 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */
274 udelay(10);
275
276 writel(0x4, ddr_regs + AR71XX_DDR_REG_CONTROL); /* Auto Refresh */
277 udelay(10);
278
279 /* Issue MRS to remove DLL out-of-reset */
280 writel(mod_val, ddr_regs + AR71XX_DDR_REG_MODE);
281 udelay(100);
282
283 writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); /* MR write */
284 udelay(100);
285
286 writel(CFG_DDR2_EXT_MODE_VAL1, ddr_regs + AR71XX_DDR_REG_EMR);
287 udelay(100);
288
289 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
290 udelay(100);
291
292 writel(CFG_DDR2_EXT_MODE_VAL2, ddr_regs + AR71XX_DDR_REG_EMR);
293 udelay(100);
294
295 writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); /* EMR write */
296 udelay(100);
297
298 writel(CFG_DDR2_REFRESH_VAL, ddr_regs + AR71XX_DDR_REG_REFRESH);
299 udelay(100);
300
301 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
302 writel(tap_val, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
303 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL2);
304 writel(tap_val, ddr_regs + QCA956X_DDR_REG_TAP_CTRL3);
305
306 writel(0x633c8176, srif_regs + QCA956X_SRIF_PMU1_REG);
307 /* Set DDR2 Voltage to 1.8 volts */
308 writel(PMU2_SWREGMSB_SET(0x40) | PMU2_PGM_SET(0x1),
309 srif_regs + QCA956X_SRIF_PMU2_REG);
310 }
311