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/dports/editors/fpc-ide/fpc-3.2.2/rtl/embedded/arm/
H A Dstm32f401xx.pp545 DMA2_BASE = AHB1PERIPH_BASE + $6400;
546 DMA2_Stream0_BASE = DMA2_BASE + $010;
547 DMA2_Stream1_BASE = DMA2_BASE + $028;
548 DMA2_Stream2_BASE = DMA2_BASE + $040;
549 DMA2_Stream3_BASE = DMA2_BASE + $058;
550 DMA2_Stream4_BASE = DMA2_BASE + $070;
551 DMA2_Stream5_BASE = DMA2_BASE + $088;
552 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
553 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
614 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f411xe.pp547 DMA2_BASE = AHB1PERIPH_BASE + $6400;
548 DMA2_Stream0_BASE = DMA2_BASE + $010;
549 DMA2_Stream1_BASE = DMA2_BASE + $028;
550 DMA2_Stream2_BASE = DMA2_BASE + $040;
551 DMA2_Stream3_BASE = DMA2_BASE + $058;
552 DMA2_Stream4_BASE = DMA2_BASE + $070;
553 DMA2_Stream5_BASE = DMA2_BASE + $088;
554 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
555 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
617 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f407xx.pp770 DMA2_BASE = AHB1PERIPH_BASE + $6400;
771 DMA2_Stream0_BASE = DMA2_BASE + $010;
772 DMA2_Stream1_BASE = DMA2_BASE + $028;
773 DMA2_Stream2_BASE = DMA2_BASE + $040;
774 DMA2_Stream3_BASE = DMA2_BASE + $058;
775 DMA2_Stream4_BASE = DMA2_BASE + $070;
776 DMA2_Stream5_BASE = DMA2_BASE + $088;
777 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
778 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
867 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f446xx.pp777 DMA2_BASE = AHB1PERIPH_BASE + $6400;
778 DMA2_Stream0_BASE = DMA2_BASE + $010;
779 DMA2_Stream1_BASE = DMA2_BASE + $028;
780 DMA2_Stream2_BASE = DMA2_BASE + $040;
781 DMA2_Stream3_BASE = DMA2_BASE + $058;
782 DMA2_Stream4_BASE = DMA2_BASE + $070;
783 DMA2_Stream5_BASE = DMA2_BASE + $088;
784 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
785 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
875 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f429xx.pp880 DMA2_BASE = AHB1PERIPH_BASE + $6400;
881 DMA2_Stream0_BASE = DMA2_BASE + $010;
882 DMA2_Stream1_BASE = DMA2_BASE + $028;
883 DMA2_Stream2_BASE = DMA2_BASE + $040;
884 DMA2_Stream3_BASE = DMA2_BASE + $058;
885 DMA2_Stream4_BASE = DMA2_BASE + $070;
886 DMA2_Stream5_BASE = DMA2_BASE + $088;
887 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
888 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
992 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f745.pp996 DMA2_BASE = (AHB1PERIPH_BASE + $6400);
997 DMA2_Stream0_BASE = (DMA2_BASE + $010);
998 DMA2_Stream1_BASE = (DMA2_BASE + $028);
999 DMA2_Stream2_BASE = (DMA2_BASE + $040);
1000 DMA2_Stream3_BASE = (DMA2_BASE + $058);
1001 DMA2_Stream4_BASE = (DMA2_BASE + $070);
1002 DMA2_Stream5_BASE = (DMA2_BASE + $088);
1003 DMA2_Stream6_BASE = (DMA2_BASE + $0A0);
1004 DMA2_Stream7_BASE = (DMA2_BASE + $0B8);
1120 DMA2: DMA_TypeDef absolute DMA2_BASE;
/dports/lang/fpc-source/fpc-3.2.2/rtl/embedded/arm/
H A Dstm32f401xx.pp545 DMA2_BASE = AHB1PERIPH_BASE + $6400;
546 DMA2_Stream0_BASE = DMA2_BASE + $010;
547 DMA2_Stream1_BASE = DMA2_BASE + $028;
548 DMA2_Stream2_BASE = DMA2_BASE + $040;
549 DMA2_Stream3_BASE = DMA2_BASE + $058;
550 DMA2_Stream4_BASE = DMA2_BASE + $070;
551 DMA2_Stream5_BASE = DMA2_BASE + $088;
552 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
553 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
614 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f411xe.pp547 DMA2_BASE = AHB1PERIPH_BASE + $6400;
548 DMA2_Stream0_BASE = DMA2_BASE + $010;
549 DMA2_Stream1_BASE = DMA2_BASE + $028;
550 DMA2_Stream2_BASE = DMA2_BASE + $040;
551 DMA2_Stream3_BASE = DMA2_BASE + $058;
552 DMA2_Stream4_BASE = DMA2_BASE + $070;
553 DMA2_Stream5_BASE = DMA2_BASE + $088;
554 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
555 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
617 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f407xx.pp770 DMA2_BASE = AHB1PERIPH_BASE + $6400;
771 DMA2_Stream0_BASE = DMA2_BASE + $010;
772 DMA2_Stream1_BASE = DMA2_BASE + $028;
773 DMA2_Stream2_BASE = DMA2_BASE + $040;
774 DMA2_Stream3_BASE = DMA2_BASE + $058;
775 DMA2_Stream4_BASE = DMA2_BASE + $070;
776 DMA2_Stream5_BASE = DMA2_BASE + $088;
777 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
778 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
867 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f446xx.pp777 DMA2_BASE = AHB1PERIPH_BASE + $6400;
778 DMA2_Stream0_BASE = DMA2_BASE + $010;
779 DMA2_Stream1_BASE = DMA2_BASE + $028;
780 DMA2_Stream2_BASE = DMA2_BASE + $040;
781 DMA2_Stream3_BASE = DMA2_BASE + $058;
782 DMA2_Stream4_BASE = DMA2_BASE + $070;
783 DMA2_Stream5_BASE = DMA2_BASE + $088;
784 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
785 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
875 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f429xx.pp880 DMA2_BASE = AHB1PERIPH_BASE + $6400;
881 DMA2_Stream0_BASE = DMA2_BASE + $010;
882 DMA2_Stream1_BASE = DMA2_BASE + $028;
883 DMA2_Stream2_BASE = DMA2_BASE + $040;
884 DMA2_Stream3_BASE = DMA2_BASE + $058;
885 DMA2_Stream4_BASE = DMA2_BASE + $070;
886 DMA2_Stream5_BASE = DMA2_BASE + $088;
887 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
888 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
992 DMA2 : TDMA_Registers absolute DMA2_BASE;
/dports/lang/fpc/fpc-3.2.2/rtl/embedded/arm/
H A Dstm32f401xx.pp545 DMA2_BASE = AHB1PERIPH_BASE + $6400;
546 DMA2_Stream0_BASE = DMA2_BASE + $010;
547 DMA2_Stream1_BASE = DMA2_BASE + $028;
548 DMA2_Stream2_BASE = DMA2_BASE + $040;
549 DMA2_Stream3_BASE = DMA2_BASE + $058;
550 DMA2_Stream4_BASE = DMA2_BASE + $070;
551 DMA2_Stream5_BASE = DMA2_BASE + $088;
552 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
553 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
614 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f411xe.pp547 DMA2_BASE = AHB1PERIPH_BASE + $6400;
548 DMA2_Stream0_BASE = DMA2_BASE + $010;
549 DMA2_Stream1_BASE = DMA2_BASE + $028;
550 DMA2_Stream2_BASE = DMA2_BASE + $040;
551 DMA2_Stream3_BASE = DMA2_BASE + $058;
552 DMA2_Stream4_BASE = DMA2_BASE + $070;
553 DMA2_Stream5_BASE = DMA2_BASE + $088;
554 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
555 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
617 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f407xx.pp770 DMA2_BASE = AHB1PERIPH_BASE + $6400;
771 DMA2_Stream0_BASE = DMA2_BASE + $010;
772 DMA2_Stream1_BASE = DMA2_BASE + $028;
773 DMA2_Stream2_BASE = DMA2_BASE + $040;
774 DMA2_Stream3_BASE = DMA2_BASE + $058;
775 DMA2_Stream4_BASE = DMA2_BASE + $070;
776 DMA2_Stream5_BASE = DMA2_BASE + $088;
777 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
778 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
867 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f446xx.pp777 DMA2_BASE = AHB1PERIPH_BASE + $6400;
778 DMA2_Stream0_BASE = DMA2_BASE + $010;
779 DMA2_Stream1_BASE = DMA2_BASE + $028;
780 DMA2_Stream2_BASE = DMA2_BASE + $040;
781 DMA2_Stream3_BASE = DMA2_BASE + $058;
782 DMA2_Stream4_BASE = DMA2_BASE + $070;
783 DMA2_Stream5_BASE = DMA2_BASE + $088;
784 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
785 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
875 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f429xx.pp880 DMA2_BASE = AHB1PERIPH_BASE + $6400;
881 DMA2_Stream0_BASE = DMA2_BASE + $010;
882 DMA2_Stream1_BASE = DMA2_BASE + $028;
883 DMA2_Stream2_BASE = DMA2_BASE + $040;
884 DMA2_Stream3_BASE = DMA2_BASE + $058;
885 DMA2_Stream4_BASE = DMA2_BASE + $070;
886 DMA2_Stream5_BASE = DMA2_BASE + $088;
887 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
888 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
992 DMA2 : TDMA_Registers absolute DMA2_BASE;
/dports/lang/fpc-utils/fpc-3.2.2/rtl/embedded/arm/
H A Dstm32f401xx.pp545 DMA2_BASE = AHB1PERIPH_BASE + $6400;
546 DMA2_Stream0_BASE = DMA2_BASE + $010;
547 DMA2_Stream1_BASE = DMA2_BASE + $028;
548 DMA2_Stream2_BASE = DMA2_BASE + $040;
549 DMA2_Stream3_BASE = DMA2_BASE + $058;
550 DMA2_Stream4_BASE = DMA2_BASE + $070;
551 DMA2_Stream5_BASE = DMA2_BASE + $088;
552 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
553 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
614 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f411xe.pp547 DMA2_BASE = AHB1PERIPH_BASE + $6400;
548 DMA2_Stream0_BASE = DMA2_BASE + $010;
549 DMA2_Stream1_BASE = DMA2_BASE + $028;
550 DMA2_Stream2_BASE = DMA2_BASE + $040;
551 DMA2_Stream3_BASE = DMA2_BASE + $058;
552 DMA2_Stream4_BASE = DMA2_BASE + $070;
553 DMA2_Stream5_BASE = DMA2_BASE + $088;
554 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
555 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
617 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f407xx.pp770 DMA2_BASE = AHB1PERIPH_BASE + $6400;
771 DMA2_Stream0_BASE = DMA2_BASE + $010;
772 DMA2_Stream1_BASE = DMA2_BASE + $028;
773 DMA2_Stream2_BASE = DMA2_BASE + $040;
774 DMA2_Stream3_BASE = DMA2_BASE + $058;
775 DMA2_Stream4_BASE = DMA2_BASE + $070;
776 DMA2_Stream5_BASE = DMA2_BASE + $088;
777 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
778 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
867 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f446xx.pp777 DMA2_BASE = AHB1PERIPH_BASE + $6400;
778 DMA2_Stream0_BASE = DMA2_BASE + $010;
779 DMA2_Stream1_BASE = DMA2_BASE + $028;
780 DMA2_Stream2_BASE = DMA2_BASE + $040;
781 DMA2_Stream3_BASE = DMA2_BASE + $058;
782 DMA2_Stream4_BASE = DMA2_BASE + $070;
783 DMA2_Stream5_BASE = DMA2_BASE + $088;
784 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
785 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
875 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f429xx.pp880 DMA2_BASE = AHB1PERIPH_BASE + $6400;
881 DMA2_Stream0_BASE = DMA2_BASE + $010;
882 DMA2_Stream1_BASE = DMA2_BASE + $028;
883 DMA2_Stream2_BASE = DMA2_BASE + $040;
884 DMA2_Stream3_BASE = DMA2_BASE + $058;
885 DMA2_Stream4_BASE = DMA2_BASE + $070;
886 DMA2_Stream5_BASE = DMA2_BASE + $088;
887 DMA2_Stream6_BASE = DMA2_BASE + $0A0;
888 DMA2_Stream7_BASE = DMA2_BASE + $0B8;
992 DMA2 : TDMA_Registers absolute DMA2_BASE;
H A Dstm32f745.pp996 DMA2_BASE = (AHB1PERIPH_BASE + $6400);
997 DMA2_Stream0_BASE = (DMA2_BASE + $010);
998 DMA2_Stream1_BASE = (DMA2_BASE + $028);
999 DMA2_Stream2_BASE = (DMA2_BASE + $040);
1000 DMA2_Stream3_BASE = (DMA2_BASE + $058);
1001 DMA2_Stream4_BASE = (DMA2_BASE + $070);
1002 DMA2_Stream5_BASE = (DMA2_BASE + $088);
1003 DMA2_Stream6_BASE = (DMA2_BASE + $0A0);
1004 DMA2_Stream7_BASE = (DMA2_BASE + $0B8);
1120 DMA2: DMA_TypeDef absolute DMA2_BASE;
/dports/audio/libmikmod/libmikmod-3.3.11.1/drivers/dos/
H A Ddosdma.h26 #define DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
/dports/audio/wildmidi/wildmidi-wildmidi-0.4.2/djgpp/
H A Ddosdma.h28 #define DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
/dports/devel/openocd/openocd-0.11.0/tcl/chip/st/stm32/
H A Dstm32_regs.tcl66 set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]

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