/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
H A D | soc.c | 44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 109 val = mmio_read_32(FIREWALL_DDR_BASE + in sgrf_init() 112 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 115 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
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/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
H A D | soc.c | 44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 109 val = mmio_read_32(FIREWALL_DDR_BASE + in sgrf_init() 112 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 115 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
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/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
H A D | soc.c | 44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 109 val = mmio_read_32(FIREWALL_DDR_BASE + in sgrf_init() 112 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 115 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
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/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
H A D | soc.c | 44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 109 val = mmio_read_32(FIREWALL_DDR_BASE + in sgrf_init() 112 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 115 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
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/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/drivers/soc/ |
H A D | soc.c | 44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE, 109 val = mmio_read_32(FIREWALL_DDR_BASE + in sgrf_init() 112 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 115 mmio_write_32(FIREWALL_DDR_BASE + in sgrf_init() 122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0); in sgrf_init()
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/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/secure/ |
H A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
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/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/secure/ |
H A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
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/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/secure/ |
H A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
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/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/secure/ |
H A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
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/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/px30/drivers/secure/ |
H A D | secure.c | 39 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region() 44 val = mmio_read_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_CON_REG); in secure_ddr_region() 46 mmio_write_32(FIREWALL_DDR_BASE + in secure_ddr_region()
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/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/rk3328/ |
H A D | rk3328_def.h | 79 #define FIREWALL_DDR_BASE 0xff7c0000 macro
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/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/rk3328/ |
H A D | rk3328_def.h | 79 #define FIREWALL_DDR_BASE 0xff7c0000 macro
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/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/rk3328/ |
H A D | rk3328_def.h | 79 #define FIREWALL_DDR_BASE 0xff7c0000 macro
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/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/rk3328/ |
H A D | rk3328_def.h | 79 #define FIREWALL_DDR_BASE 0xff7c0000 macro
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/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/rk3328/ |
H A D | rk3328_def.h | 79 #define FIREWALL_DDR_BASE 0xff7c0000 macro
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/dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/plat/rockchip/px30/ |
H A D | px30_def.h | 109 #define FIREWALL_DDR_BASE 0xff534000 macro
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/dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/plat/rockchip/px30/ |
H A D | px30_def.h | 109 #define FIREWALL_DDR_BASE 0xff534000 macro
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/dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/plat/rockchip/px30/ |
H A D | px30_def.h | 109 #define FIREWALL_DDR_BASE 0xff534000 macro
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/dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/plat/rockchip/px30/ |
H A D | px30_def.h | 109 #define FIREWALL_DDR_BASE 0xff534000 macro
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/dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/plat/rockchip/px30/ |
H A D | px30_def.h | 109 #define FIREWALL_DDR_BASE 0xff534000 macro
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