1 /*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <platform_def.h>
8
9 #include <arch_helpers.h>
10 #include <common/debug.h>
11 #include <drivers/console.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14
15 #include <ddr_parameter.h>
16 #include <plat_private.h>
17 #include <rk3328_def.h>
18 #include <soc.h>
19
20 /* Table of regions to map using the MMU. */
21 const mmap_region_t plat_rk_mmap[] = {
22 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
23 MT_DEVICE | MT_RW | MT_SECURE),
24 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
25 MT_DEVICE | MT_RW | MT_SECURE),
26 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
27 MT_DEVICE | MT_RW | MT_SECURE),
28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
29 MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
31 MT_DEVICE | MT_RW | MT_SECURE),
32 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
33 MT_DEVICE | MT_RW | MT_SECURE),
34 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
35 MT_DEVICE | MT_RW | MT_SECURE),
36 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
37 MT_DEVICE | MT_RW | MT_SECURE),
38 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
39 MT_DEVICE | MT_RW | MT_SECURE),
40 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
41 MT_DEVICE | MT_RW | MT_SECURE),
42 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
43 MT_DEVICE | MT_RW | MT_SECURE),
44 MAP_REGION_FLAT(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE,
45 MT_DEVICE | MT_RW | MT_SECURE),
46 MAP_REGION_FLAT(FIREWALL_CFG_BASE, FIREWALL_CFG_SIZE,
47 MT_DEVICE | MT_RW | MT_SECURE),
48 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
49 MT_DEVICE | MT_RW | MT_SECURE),
50 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
51 MT_DEVICE | MT_RW | MT_SECURE),
52 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
53 MT_MEMORY | MT_RW | MT_SECURE),
54 MAP_REGION_FLAT(SHARE_MEM_BASE, SHARE_MEM_SIZE,
55 MT_DEVICE | MT_RW | MT_SECURE),
56 MAP_REGION_FLAT(DDR_GRF_BASE, DDR_GRF_SIZE,
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE,
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(PWM_BASE, PWM_SIZE,
61 MT_DEVICE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(DDR_PARAM_BASE, DDR_PARAM_SIZE,
63 MT_DEVICE | MT_RW | MT_SECURE),
64 MAP_REGION_FLAT(EFUSE8_BASE, EFUSE8_SIZE,
65 MT_DEVICE | MT_RW | MT_SECURE),
66 MAP_REGION_FLAT(EFUSE32_BASE, EFUSE32_SIZE,
67 MT_DEVICE | MT_RW | MT_SECURE),
68 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE,
69 MT_DEVICE | MT_RW | MT_SECURE),
70 MAP_REGION_FLAT(SERVER_MSCH_BASE, SERVER_MSCH_SIZE,
71 MT_DEVICE | MT_RW | MT_SECURE),
72 MAP_REGION_FLAT(DDR_MONITOR_BASE, DDR_MONITOR_SIZE,
73 MT_DEVICE | MT_RW | MT_SECURE),
74 MAP_REGION_FLAT(VOP_BASE, VOP_SIZE,
75 MT_DEVICE | MT_RW | MT_SECURE),
76
77 { 0 }
78 };
79
80 /* The RockChip power domain tree descriptor */
81 const unsigned char rockchip_power_domain_tree_desc[] = {
82 /* No of root nodes */
83 PLATFORM_SYSTEM_COUNT,
84 /* No of children for the root node */
85 PLATFORM_CLUSTER_COUNT,
86 /* No of children for the first cluster node */
87 PLATFORM_CLUSTER0_CORE_COUNT,
88 };
89
secure_timer_init(void)90 void secure_timer_init(void)
91 {
92 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff);
93 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff);
94 /* auto reload & enable the timer */
95 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN);
96 }
97
sgrf_init(void)98 void sgrf_init(void)
99 {
100 #ifdef PLAT_RK_SECURE_DDR_MINILOADER
101 uint32_t i, val;
102 struct param_ddr_usage usg;
103
104 /* general secure regions */
105 usg = ddr_region_usage_parse(DDR_PARAM_BASE,
106 PLAT_MAX_DDR_CAPACITY_MB);
107 for (i = 0; i < usg.s_nr; i++) {
108 /* enable secure */
109 val = mmio_read_32(FIREWALL_DDR_BASE +
110 FIREWALL_DDR_FW_DDR_CON_REG);
111 val |= BIT(7 - i);
112 mmio_write_32(FIREWALL_DDR_BASE +
113 FIREWALL_DDR_FW_DDR_CON_REG, val);
114 /* map top and base */
115 mmio_write_32(FIREWALL_DDR_BASE +
116 FIREWALL_DDR_FW_DDR_RGN(7 - i),
117 RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
118 }
119 #endif
120
121 /* set ddr rgn0_top and rga0_top as 0 */
122 mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
123
124 /* set all slave ip into no-secure, except stimer */
125 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(0),
126 SGRF_SLV_S_ALL_NS);
127 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(1),
128 SGRF_SLV_S_ALL_NS);
129 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(2),
130 SGRF_SLV_S_ALL_NS | STIMER_S);
131 mmio_write_32(FIREWALL_CFG_BASE + FIREWALL_CFG_FW_SYS_CON(3),
132 SGRF_SLV_S_ALL_NS);
133
134 /* set all master ip into no-secure */
135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000);
136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS);
137 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS);
138
139 /* set DMAC into no-secure */
140 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(3), DMA_IRQ_BOOT_NS);
141 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(4), DMA_PERI_CH_NS_15_0);
142 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_PERI_CH_NS_19_16);
143 mmio_write_32(SGRF_BASE + SGRF_DMAC_CON(5), DMA_MANAGER_BOOT_NS);
144
145 /* soft reset dma before use */
146 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ);
147 udelay(5);
148 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS);
149 }
150
plat_rockchip_soc_init(void)151 void plat_rockchip_soc_init(void)
152 {
153 secure_timer_init();
154 sgrf_init();
155
156 NOTICE("BL31:Rockchip release version: v%d.%d\n",
157 MAJOR_VERSION, MINOR_VERSION);
158 }
159