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Searched refs:Get_Right_Limit (Results 1 – 19 of 19) sorted by relevance

/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/
H A Dvhdl-evaluation.adb294 Set_Right_Limit (Res, Get_Right_Limit (Range_Expr));
532 Rng_Start := Get_Right_Limit (Rng);
2343 Lit := Create_Bound (Get_Right_Limit (Rng));
2799 Right := Eval_Pos (Get_Right_Limit (Rng));
3088 (Get_Right_Limit (Get_Range_Constraint (Index)));
3438 or else Val > Eval_Pos (Get_Right_Limit (Bound))
3465 Right := Get_Value (Get_Right_Limit (Bound));
3705 R := Eval_Pos (Get_Right_Limit (Range_Constraint));
3766 Right := Eval_Pos (Get_Right_Limit (Constraint));
3805 Right := Eval_Pos (Get_Right_Limit (Rng));
[all …]
H A Dvhdl-utils.adb914 Free_Recursive (Get_Right_Limit (N));
1582 High := Get_Right_Limit (Arange);
1585 Low := Get_Right_Limit (Arange);
1595 return Get_Right_Limit (Arange);
1603 return Get_Right_Limit (Arange);
H A Dvhdl-std_package.adb1424 Change_Unit (Get_Right_Limit (Rng), Prim);
1430 Change_Unit (Get_Right_Limit (Rng), Prim);
H A Dvhdl-sem_assocs.adb560 or else not Eval_Is_Eq (Get_Right_Limit (Src_Range),
561 Get_Right_Limit (Dst_Range))
H A Dvhdl-sem.adb1614 or else not Are_Trees_Equal (Get_Right_Limit (Left),
1615 Get_Right_Limit (Right))
H A Dvhdl-sem_types.adb332 Set_Type (Get_Right_Limit (Rng), Base_Type);
441 Lit := Get_Right_Limit (Range_Expr1);
H A Dvhdl-canon.adb221 (Get_Right_Limit (Expr), Sensitivity_List, False);
650 Canon_Expression (Get_Right_Limit (Expr));
H A Dvhdl-nodes.ads8140 function Get_Right_Limit (Decl : Iir_Range_Expression) return Iir; subprogspec
H A Dvhdl-nodes.adb3772 function Get_Right_Limit (Decl : Iir_Range_Expression) return Iir is subprogram
3778 end Get_Right_Limit;
H A Dvhdl-prints.adb328 Get_Right_Limit (Rng)));
H A Dvhdl-nodes_meta.adb6169 return Get_Right_Limit (N);
/dports/cad/ghdl/ghdl-1.0.0/src/synth/
H A Dsynth-decls.adb308 R := Get_Value (Get_Right_Limit (Cst));
322 R := Get_Fp_Value (Get_Right_Limit (Cst));
H A Dsynth-expr.adb447 R := Synth_Expression_With_Basetype (Syn_Inst, Get_Right_Limit (Rng));
475 R := Synth_Expression (Syn_Inst, Get_Right_Limit (Rng));
1509 (Syn_Inst, Get_Right_Limit (Expr));
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/translate/
H A Dtrans-chap14.adb580 (Get_Right_Limit (Get_Range_Constraint (Time_Subtype_Definition)));
H A Dtrans-chap7.adb637 Right := Chap7.Translate_Static_Expression (Get_Right_Limit (Expr),
682 Right := Chap7.Translate_Expression (Get_Right_Limit (Expr));
736 Right := Chap7.Translate_Expression (Get_Right_Limit (Expr));
4606 Right_Pat := Get_Length_Pattern (Get_Right_Limit (Rng), True);
H A Dtrans-chap3.adb2164 and then Get_Right_Limit (Rng) = Get_Right_Limit (Tm_Rng)
/dports/cad/ghdl/ghdl-1.0.0/src/vhdl/simulate/
H A Dsimul-elaboration.adb858 Execute_Expression (Instance, Get_Right_Limit (Rc)),
890 Execute_Expression (Instance, Get_Right_Limit (Rc)),
H A Dsimul-execution.adb2307 Execute_Expression (Block, Get_Right_Limit (Prefix)),
/dports/cad/ghdl/ghdl-1.0.0/pyGHDL/libghdl/vhdl/
H A Dnodes.py2182 Get_Right_Limit = libghdl.vhdl__nodes__get_right_limit variable