1-- Create declarations for synthesis. 2-- Copyright (C) 2017 Tristan Gingold 3-- 4-- This file is part of GHDL. 5-- 6-- This program is free software; you can redistribute it and/or modify 7-- it under the terms of the GNU General Public License as published by 8-- the Free Software Foundation; either version 2 of the License, or 9-- (at your option) any later version. 10-- 11-- This program is distributed in the hope that it will be useful, 12-- but WITHOUT ANY WARRANTY; without even the implied warranty of 13-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14-- GNU General Public License for more details. 15-- 16-- You should have received a copy of the GNU General Public License 17-- along with this program; if not, write to the Free Software 18-- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 19-- MA 02110-1301, USA. 20 21with Types; use Types; 22with Mutils; use Mutils; 23with Std_Names; 24 25with Netlists.Builders; use Netlists.Builders; 26with Netlists.Folds; use Netlists.Folds; 27with Netlists.Utils; use Netlists.Utils; 28with Netlists.Gates; 29 30with Vhdl.Errors; 31with Vhdl.Utils; use Vhdl.Utils; 32with Vhdl.Std_Package; 33with Vhdl.Ieee.Std_Logic_1164; 34 35with Synth.Environment; use Synth.Environment; 36with Synth.Expr; use Synth.Expr; 37with Synth.Stmts; 38with Synth.Source; use Synth.Source; 39with Synth.Errors; use Synth.Errors; 40with Synth.Files_Operations; 41with Synth.Values; use Synth.Values; 42 43package body Synth.Decls is 44 procedure Create_Var_Wire 45 (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Init : Valtyp) 46 is 47 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 48 Vt : constant Valtyp := Get_Value (Syn_Inst, Decl); 49 Value : Net; 50 Ival : Net; 51 W : Width; 52 Name : Sname; 53 begin 54 case Vt.Val.Kind is 55 when Value_Wire => 56 -- FIXME: get the width directly from the wire ? 57 W := Get_Type_Width (Vt.Typ); 58 Name := New_Sname_User (Get_Identifier (Decl), 59 Get_Sname (Syn_Inst)); 60 if Init /= No_Valtyp then 61 Ival := Get_Net (Ctxt, Init); 62 pragma Assert (Get_Width (Ival) = W); 63 Value := Build_Isignal (Ctxt, Name, Ival); 64 else 65 Value := Build_Signal (Ctxt, Name, W); 66 end if; 67 Set_Location (Value, Decl); 68 Set_Wire_Gate (Vt.Val.W, Value); 69 when others => 70 raise Internal_Error; 71 end case; 72 end Create_Var_Wire; 73 74 function Type_To_Param_Type (Atype : Node) return Param_Type 75 is 76 use Vhdl.Std_Package; 77 Btype : constant Node := Get_Base_Type (Atype); 78 begin 79 if Btype = String_Type_Definition then 80 return Param_Pval_String; 81 elsif Btype = Time_Type_Definition then 82 return Param_Pval_Time_Ps; 83 else 84 case Get_Kind (Btype) is 85 when Iir_Kind_Integer_Type_Definition => 86 return Param_Pval_Integer; 87 when Iir_Kind_Floating_Type_Definition => 88 return Param_Pval_Real; 89 when others => 90 return Param_Pval_Vector; 91 end case; 92 end if; 93 end Type_To_Param_Type; 94 95 function Memtyp_To_Pval (Mt : Memtyp) return Pval 96 is 97 Len : constant Uns32 := (Mt.Typ.W + 31) / 32; 98 pragma Assert (Len > 0); 99 Vec : Logvec_Array_Acc; 100 Off : Uns32; 101 Has_Zx : Boolean; 102 Pv : Pval; 103 begin 104 Vec := new Logvec_Array'(0 .. Digit_Index (Len - 1) => (0, 0)); 105 Off := 0; 106 Has_Zx := False; 107 Value2logvec (Mt, 0, Mt.Typ.W, Vec.all, Off, Has_Zx); 108 pragma Assert (Off = Mt.Typ.W); 109 if Has_Zx then 110 Pv := Create_Pval4 (Mt.Typ.W); 111 else 112 Pv := Create_Pval2 (Mt.Typ.W); 113 end if; 114 for I in 0 .. Len - 1 loop 115 Write_Pval (Pv, I, Vec (Digit_Index (I))); 116 end loop; 117 Free_Logvec_Array (Vec); 118 return Pv; 119 end Memtyp_To_Pval; 120 121 procedure Synth_Subtype_Indication_If_Anonymous 122 (Syn_Inst : Synth_Instance_Acc; Atype : Node) is 123 begin 124 if Get_Type_Declarator (Atype) = Null_Node then 125 Synth_Subtype_Indication (Syn_Inst, Atype); 126 end if; 127 end Synth_Subtype_Indication_If_Anonymous; 128 129 function Synth_Subtype_Indication_If_Anonymous 130 (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Type_Acc is 131 begin 132 if Get_Type_Declarator (Atype) = Null_Node then 133 return Synth_Subtype_Indication (Syn_Inst, Atype); 134 else 135 return Get_Subtype_Object (Syn_Inst, Atype); 136 end if; 137 end Synth_Subtype_Indication_If_Anonymous; 138 139 function Synth_Array_Type_Definition 140 (Syn_Inst : Synth_Instance_Acc; Def : Node) return Type_Acc 141 is 142 El_Type : constant Node := Get_Element_Subtype (Def); 143 Ndims : constant Natural := Get_Nbr_Dimensions (Def); 144 El_Typ : Type_Acc; 145 Typ : Type_Acc; 146 begin 147 Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); 148 El_Typ := Get_Subtype_Object (Syn_Inst, El_Type); 149 150 if El_Typ.Kind in Type_Nets and then Ndims = 1 then 151 Typ := Create_Unbounded_Vector (El_Typ); 152 else 153 Typ := Create_Unbounded_Array (Dim_Type (Ndims), El_Typ); 154 end if; 155 return Typ; 156 end Synth_Array_Type_Definition; 157 158 function Synth_Record_Type_Definition 159 (Syn_Inst : Synth_Instance_Acc; Def : Node) return Type_Acc 160 is 161 El_List : constant Node_Flist := Get_Elements_Declaration_List (Def); 162 Rec_Els : Rec_El_Array_Acc; 163 El : Node; 164 El_Type : Node; 165 El_Typ : Type_Acc; 166 begin 167 Rec_Els := Create_Rec_El_Array 168 (Iir_Index32 (Get_Nbr_Elements (El_List))); 169 170 for I in Flist_First .. Flist_Last (El_List) loop 171 El := Get_Nth_Element (El_List, I); 172 El_Type := Get_Type (El); 173 El_Typ := Synth_Subtype_Indication_If_Anonymous (Syn_Inst, El_Type); 174 Rec_Els.E (Iir_Index32 (I + 1)).Typ := El_Typ; 175 end loop; 176 177 if not Is_Fully_Constrained_Type (Def) then 178 return Create_Unbounded_Record (Rec_Els); 179 else 180 return Create_Record_Type (Rec_Els); 181 end if; 182 end Synth_Record_Type_Definition; 183 184 function Synth_Access_Type_Definition 185 (Syn_Inst : Synth_Instance_Acc; Def : Node) return Type_Acc 186 is 187 Des_Type : constant Node := Get_Designated_Type (Def); 188 Des_Typ : Type_Acc; 189 Typ : Type_Acc; 190 begin 191 Synth_Subtype_Indication_If_Anonymous (Syn_Inst, Des_Type); 192 Des_Typ := Get_Subtype_Object (Syn_Inst, Des_Type); 193 194 Typ := Create_Access_Type (Des_Typ); 195 return Typ; 196 end Synth_Access_Type_Definition; 197 198 function Synth_File_Type_Definition 199 (Syn_Inst : Synth_Instance_Acc; Def : Node) return Type_Acc 200 is 201 File_Type : constant Node := Get_Type (Get_File_Type_Mark (Def)); 202 File_Typ : Type_Acc; 203 Typ : Type_Acc; 204 Sig : String_Acc; 205 begin 206 File_Typ := Get_Subtype_Object (Syn_Inst, File_Type); 207 208 if Get_Text_File_Flag (Def) 209 or else 210 Get_Kind (File_Type) in Iir_Kinds_Scalar_Type_And_Subtype_Definition 211 then 212 Sig := null; 213 else 214 declare 215 Sig_Str : String (1 .. Get_File_Signature_Length (File_Type) + 2); 216 Off : Natural := Sig_Str'First; 217 begin 218 Get_File_Signature (File_Type, Sig_Str, Off); 219 Sig_Str (Off + 0) := '.'; 220 Sig_Str (Off + 1) := ASCII.NUL; 221 Sig := new String'(Sig_Str); 222 end; 223 end if; 224 225 Typ := Create_File_Type (File_Typ); 226 Typ.File_Signature := Sig; 227 228 return Typ; 229 end Synth_File_Type_Definition; 230 231 function Scalar_Size_To_Size (Def : Node) return Size_Type is 232 begin 233 case Get_Scalar_Size (Def) is 234 when Scalar_8 => 235 return 1; 236 when Scalar_16 => 237 return 2; 238 when Scalar_32 => 239 return 4; 240 when Scalar_64 => 241 return 8; 242 end case; 243 end Scalar_Size_To_Size; 244 245 procedure Synth_Type_Definition (Syn_Inst : Synth_Instance_Acc; Def : Node) 246 is 247 Typ : Type_Acc; 248 begin 249 case Get_Kind (Def) is 250 when Iir_Kind_Enumeration_Type_Definition => 251 if Def = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type 252 or else Def = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Type 253 then 254 Typ := Logic_Type; 255 elsif Def = Vhdl.Std_Package.Boolean_Type_Definition then 256 Typ := Boolean_Type; 257 elsif Def = Vhdl.Std_Package.Bit_Type_Definition then 258 Typ := Bit_Type; 259 else 260 declare 261 Nbr_El : constant Natural := 262 Get_Nbr_Elements (Get_Enumeration_Literal_List (Def)); 263 Rng : Discrete_Range_Type; 264 W : Width; 265 begin 266 W := Uns32 (Clog2 (Uns64 (Nbr_El))); 267 Rng := (Dir => Dir_To, 268 Is_Signed => False, 269 Left => 0, 270 Right => Int64 (Nbr_El - 1)); 271 Typ := Create_Discrete_Type 272 (Rng, Scalar_Size_To_Size (Def), W); 273 end; 274 end if; 275 when Iir_Kind_Array_Type_Definition => 276 Typ := Synth_Array_Type_Definition (Syn_Inst, Def); 277 when Iir_Kind_Access_Type_Definition => 278 Typ := Synth_Access_Type_Definition (Syn_Inst, Def); 279 when Iir_Kind_File_Type_Definition => 280 Typ := Synth_File_Type_Definition (Syn_Inst, Def); 281 when Iir_Kind_Record_Type_Definition => 282 Typ := Synth_Record_Type_Definition (Syn_Inst, Def); 283 when Iir_Kind_Protected_Type_Declaration => 284 Synth_Declarations (Syn_Inst, Get_Declaration_Chain (Def)); 285 when others => 286 Vhdl.Errors.Error_Kind ("synth_type_definition", Def); 287 end case; 288 if Typ /= null then 289 Create_Subtype_Object (Syn_Inst, Def, Typ); 290 end if; 291 end Synth_Type_Definition; 292 293 procedure Synth_Anonymous_Type_Definition 294 (Syn_Inst : Synth_Instance_Acc; Def : Node; St : Node) 295 is 296 Typ : Type_Acc; 297 begin 298 case Get_Kind (Def) is 299 when Iir_Kind_Integer_Type_Definition 300 | Iir_Kind_Physical_Type_Definition => 301 declare 302 Cst : constant Node := Get_Range_Constraint (St); 303 L, R : Int64; 304 Rng : Discrete_Range_Type; 305 W : Width; 306 begin 307 L := Get_Value (Get_Left_Limit (Cst)); 308 R := Get_Value (Get_Right_Limit (Cst)); 309 Rng := Synth_Discrete_Range_Expression 310 (L, R, Get_Direction (Cst)); 311 W := Discrete_Range_Width (Rng); 312 Typ := Create_Discrete_Type 313 (Rng, Scalar_Size_To_Size (Def), W); 314 end; 315 when Iir_Kind_Floating_Type_Definition => 316 declare 317 Cst : constant Node := Get_Range_Constraint (St); 318 L, R : Fp64; 319 Rng : Float_Range_Type; 320 begin 321 L := Get_Fp_Value (Get_Left_Limit (Cst)); 322 R := Get_Fp_Value (Get_Right_Limit (Cst)); 323 Rng := (Get_Direction (Cst), L, R); 324 Typ := Create_Float_Type (Rng); 325 end; 326 when Iir_Kind_Array_Type_Definition => 327 Typ := Synth_Array_Type_Definition (Syn_Inst, Def); 328 when others => 329 Vhdl.Errors.Error_Kind ("synth_anonymous_type_definition", Def); 330 end case; 331 Create_Subtype_Object (Syn_Inst, Def, Typ); 332 end Synth_Anonymous_Type_Definition; 333 334 function Synth_Discrete_Range_Constraint 335 (Syn_Inst : Synth_Instance_Acc; Rng : Node) return Discrete_Range_Type 336 is 337 Res : Discrete_Range_Type; 338 begin 339 Synth_Discrete_Range (Syn_Inst, Rng, Res); 340 return Res; 341 end Synth_Discrete_Range_Constraint; 342 343 function Synth_Float_Range_Constraint 344 (Syn_Inst : Synth_Instance_Acc; Rng : Node) return Float_Range_Type is 345 begin 346 case Get_Kind (Rng) is 347 when Iir_Kind_Range_Expression => 348 -- FIXME: check range. 349 return Synth_Float_Range_Expression (Syn_Inst, Rng); 350 when others => 351 Vhdl.Errors.Error_Kind ("synth_float_range_constraint", Rng); 352 end case; 353 end Synth_Float_Range_Constraint; 354 355 function Has_Element_Subtype_Indication (Atype : Node) return Boolean is 356 begin 357 return Get_Array_Element_Constraint (Atype) /= Null_Node 358 or else 359 (Get_Resolution_Indication (Atype) /= Null_Node 360 and then 361 (Get_Kind (Get_Resolution_Indication (Atype)) 362 = Iir_Kind_Array_Element_Resolution)); 363 end Has_Element_Subtype_Indication; 364 365 function Synth_Array_Subtype_Indication 366 (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Type_Acc 367 is 368 El_Type : constant Node := Get_Element_Subtype (Atype); 369 St_Indexes : constant Node_Flist := Get_Index_Subtype_List (Atype); 370 Ptype : Node; 371 St_El : Node; 372 Btyp : Type_Acc; 373 Etyp : Type_Acc; 374 Bnds : Bound_Array_Acc; 375 begin 376 -- VHDL08 377 if Has_Element_Subtype_Indication (Atype) then 378 -- This subtype has created a new anonymous subtype for the 379 -- element. 380 Synth_Subtype_Indication (Syn_Inst, El_Type); 381 end if; 382 383 if not Get_Index_Constraint_Flag (Atype) then 384 Ptype := Get_Type (Get_Subtype_Type_Mark (Atype)); 385 if Get_Element_Subtype (Ptype) = Get_Element_Subtype (Atype) then 386 -- That's an alias. 387 -- FIXME: maybe a resolution function was added? 388 -- FIXME: also handle resolution added in element subtype. 389 return Get_Subtype_Object (Syn_Inst, Ptype); 390 end if; 391 end if; 392 393 Btyp := Get_Subtype_Object (Syn_Inst, Get_Base_Type (Atype)); 394 case Btyp.Kind is 395 when Type_Unbounded_Vector => 396 if Get_Index_Constraint_Flag (Atype) then 397 St_El := Get_Index_Type (St_Indexes, 0); 398 return Create_Vector_Type 399 (Synth_Bounds_From_Range (Syn_Inst, St_El), Btyp.Uvec_El); 400 else 401 -- An alias. 402 -- Handle vhdl08 definition of std_logic_vector from 403 -- std_ulogic_vector. 404 return Btyp; 405 end if; 406 when Type_Unbounded_Array => 407 -- FIXME: partially constrained arrays, subtype in indexes... 408 Etyp := Get_Subtype_Object (Syn_Inst, El_Type); 409 if Get_Index_Constraint_Flag (Atype) then 410 Bnds := Create_Bound_Array 411 (Dim_Type (Get_Nbr_Elements (St_Indexes))); 412 for I in Flist_First .. Flist_Last (St_Indexes) loop 413 St_El := Get_Index_Type (St_Indexes, I); 414 Bnds.D (Dim_Type (I + 1)) := 415 Synth_Bounds_From_Range (Syn_Inst, St_El); 416 end loop; 417 return Create_Array_Type (Bnds, Etyp); 418 else 419 raise Internal_Error; 420 end if; 421 when others => 422 raise Internal_Error; 423 end case; 424 end Synth_Array_Subtype_Indication; 425 426 function Synth_Subtype_Indication 427 (Syn_Inst : Synth_Instance_Acc; Atype : Node) return Type_Acc is 428 begin 429 -- TODO: handle aliases directly. 430 case Get_Kind (Atype) is 431 when Iir_Kind_Array_Subtype_Definition => 432 return Synth_Array_Subtype_Indication (Syn_Inst, Atype); 433 when Iir_Kind_Record_Subtype_Definition => 434 return Synth_Record_Type_Definition (Syn_Inst, Atype); 435 when Iir_Kind_Integer_Subtype_Definition 436 | Iir_Kind_Physical_Subtype_Definition 437 | Iir_Kind_Enumeration_Subtype_Definition => 438 declare 439 Btype : constant Type_Acc := 440 Get_Subtype_Object (Syn_Inst, Get_Base_Type (Atype)); 441 Rng : Discrete_Range_Type; 442 W : Width; 443 begin 444 if Btype.Kind in Type_Nets then 445 -- A subtype of a bit/logic type is still a bit/logic. 446 -- FIXME: bounds. 447 return Btype; 448 else 449 Rng := Synth_Discrete_Range_Constraint 450 (Syn_Inst, Get_Range_Constraint (Atype)); 451 W := Discrete_Range_Width (Rng); 452 return Create_Discrete_Type (Rng, Btype.Sz, W); 453 end if; 454 end; 455 when Iir_Kind_Floating_Subtype_Definition => 456 declare 457 Rng : Float_Range_Type; 458 begin 459 Rng := Synth_Float_Range_Constraint 460 (Syn_Inst, Get_Range_Constraint (Atype)); 461 return Create_Float_Type (Rng); 462 end; 463 when others => 464 Vhdl.Errors.Error_Kind ("synth_subtype_indication", Atype); 465 end case; 466 end Synth_Subtype_Indication; 467 468 procedure Synth_Subtype_Indication 469 (Syn_Inst : Synth_Instance_Acc; Atype : Node) 470 is 471 Typ : Type_Acc; 472 begin 473 Typ := Synth_Subtype_Indication (Syn_Inst, Atype); 474 Create_Subtype_Object (Syn_Inst, Atype, Typ); 475 end Synth_Subtype_Indication; 476 477 function Get_Declaration_Type (Decl : Node) return Node 478 is 479 Ind : constant Node := Get_Subtype_Indication (Decl); 480 Atype : Node; 481 begin 482 if Get_Is_Ref (Decl) or else Ind = Null_Iir then 483 -- A secondary declaration in a list. 484 return Null_Node; 485 end if; 486 Atype := Ind; 487 loop 488 case Get_Kind (Atype) is 489 when Iir_Kinds_Denoting_Name => 490 Atype := Get_Named_Entity (Atype); 491 when Iir_Kind_Subtype_Declaration 492 | Iir_Kind_Type_Declaration => 493 -- Type already declared, so already handled. 494 return Null_Node; 495 when Iir_Kind_Array_Subtype_Definition 496 | Iir_Kind_Record_Subtype_Definition 497 | Iir_Kind_Integer_Subtype_Definition 498 | Iir_Kind_Floating_Subtype_Definition 499 | Iir_Kind_Physical_Subtype_Definition 500 | Iir_Kind_Enumeration_Subtype_Definition => 501 return Atype; 502 when others => 503 Vhdl.Errors.Error_Kind ("get_declaration_type", Atype); 504 end case; 505 end loop; 506 end Get_Declaration_Type; 507 508 procedure Synth_Declaration_Type 509 (Syn_Inst : Synth_Instance_Acc; Decl : Node) 510 is 511 Atype : constant Node := Get_Declaration_Type (Decl); 512 begin 513 if Atype = Null_Node then 514 return; 515 end if; 516 Synth_Subtype_Indication (Syn_Inst, Atype); 517 end Synth_Declaration_Type; 518 519 procedure Synth_Constant_Declaration (Syn_Inst : Synth_Instance_Acc; 520 Decl : Node; 521 Is_Subprg : Boolean; 522 Last_Type : in out Node) 523 is 524 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 525 Deferred_Decl : constant Node := Get_Deferred_Declaration (Decl); 526 First_Decl : Node; 527 Decl_Type : Node; 528 Val : Valtyp; 529 Cst : Valtyp; 530 Obj_Type : Type_Acc; 531 begin 532 Synth_Declaration_Type (Syn_Inst, Decl); 533 if Deferred_Decl = Null_Node 534 or else Get_Deferred_Declaration_Flag (Decl) 535 then 536 -- Create the object (except for full declaration of a 537 -- deferred constant). 538 Create_Object (Syn_Inst, Decl, No_Valtyp); 539 end if; 540 -- Initialize the value (except for a deferred declaration). 541 if Get_Deferred_Declaration_Flag (Decl) then 542 return; 543 end if; 544 if Deferred_Decl = Null_Node then 545 -- A normal constant declaration 546 First_Decl := Decl; 547 else 548 -- The full declaration of a deferred constant. 549 First_Decl := Deferred_Decl; 550 end if; 551 pragma Assert (First_Decl /= Null_Node); 552 553 -- Use the type of the declaration. The type of the constant may 554 -- be derived from the value. 555 -- FIXME: what about multiple declarations ? 556 Decl_Type := Get_Subtype_Indication (Decl); 557 if Decl_Type = Null_Node then 558 Decl_Type := Last_Type; 559 else 560 if Get_Kind (Decl_Type) in Iir_Kinds_Denoting_Name then 561 -- Type mark. 562 Decl_Type := Get_Type (Get_Named_Entity (Decl_Type)); 563 end if; 564 Last_Type := Decl_Type; 565 end if; 566 Obj_Type := Get_Subtype_Object (Syn_Inst, Decl_Type); 567 Val := Synth_Expression_With_Type 568 (Syn_Inst, Get_Default_Value (Decl), Obj_Type); 569 if Val = No_Valtyp then 570 Set_Error (Syn_Inst); 571 return; 572 end if; 573 Val := Synth_Subtype_Conversion (Ctxt, Val, Obj_Type, True, Decl); 574 -- For constant functions, the value must be constant. 575 pragma Assert (not Get_Instance_Const (Syn_Inst) 576 or else Is_Static (Val.Val)); 577 case Val.Val.Kind is 578 when Value_Const 579 | Value_Alias => 580 Cst := Val; 581 when others => 582 if Is_Static (Val.Val) then 583 Cst := Create_Value_Const (Val, Decl); 584 else 585 if not Is_Subprg then 586 Error_Msg_Synth 587 (+Decl, "signals cannot be used in default value " 588 & "of this constant"); 589 end if; 590 Cst := Val; 591 end if; 592 end case; 593 Create_Object_Force (Syn_Inst, First_Decl, Cst); 594 end Synth_Constant_Declaration; 595 596 procedure Synth_Attribute_Object (Syn_Inst : Synth_Instance_Acc; 597 Attr_Value : Node; 598 Attr_Decl : Node; 599 Val : Valtyp) 600 is 601 Obj : constant Node := Get_Designated_Entity (Attr_Value); 602 Id : constant Name_Id := Get_Identifier (Attr_Decl); 603 Inst : Instance; 604 V : Valtyp; 605 Ptype : Param_Type; 606 Pv : Pval; 607 begin 608 if Id = Std_Names.Name_Foreign then 609 -- Not for synthesis. 610 return; 611 end if; 612 613 case Get_Kind (Obj) is 614 when Iir_Kind_Signal_Declaration 615 | Iir_Kind_Variable_Declaration => 616 V := Get_Value (Syn_Inst, Obj); 617 pragma Assert (V.Val.Kind = Value_Wire); 618 Inst := Get_Net_Parent (Get_Wire_Gate (V.Val.W)); 619 when Iir_Kind_Component_Instantiation_Statement => 620 -- TODO 621 return; 622 when others => 623 -- TODO: components ? 624 -- TODO: Interface_Signal ? But no instance for them. 625 Warning_Msg_Synth 626 (+Attr_Value, "attribute %i for %n is not kept in the netlist", 627 (+Attr_Decl, +Obj)); 628 return; 629 end case; 630 631 Ptype := Type_To_Param_Type (Get_Type (Attr_Decl)); 632 Pv := Memtyp_To_Pval (Get_Memtyp (Val)); 633 634 Set_Attribute (Inst, Id, Ptype, Pv); 635 end Synth_Attribute_Object; 636 637 procedure Synth_Attribute_Specification 638 (Syn_Inst : Synth_Instance_Acc; Spec : Node) 639 is 640 Attr_Decl : constant Node := 641 Get_Named_Entity (Get_Attribute_Designator (Spec)); 642 Value : Node; 643 Val : Valtyp; 644 Val_Type : Type_Acc; 645 begin 646 Val_Type := Get_Subtype_Object (Syn_Inst, Get_Type (Attr_Decl)); 647 Value := Get_Attribute_Value_Spec_Chain (Spec); 648 while Value /= Null_Iir loop 649 -- 2. The expression is evaluated to determine the value 650 -- of the attribute. 651 -- It is an error if the value of the expression does not 652 -- belong to the subtype of the attribute; if the 653 -- attribute is of an array type, then an implicit 654 -- subtype conversion is first performed on the value, 655 -- unless the attribute's subtype indication denotes an 656 -- unconstrained array type. 657 Val := Synth_Expression_With_Type 658 (Syn_Inst, Get_Expression (Spec), Val_Type); 659 -- Check_Constraints (Instance, Val, Attr_Type, Decl); 660 661 -- 3. A new instance of the designated attribute is created 662 -- and associated with each of the affected items. 663 -- 664 -- 4. Each new attribute instance is assigned the value of 665 -- the expression. 666 Create_Object (Syn_Inst, Value, Val); 667 -- Unshare (Val, Instance_Pool); 668 669 if not Get_Instance_Const (Syn_Inst) then 670 Synth_Attribute_Object (Syn_Inst, Value, Attr_Decl, Val); 671 end if; 672 673 Value := Get_Spec_Chain (Value); 674 end loop; 675 end Synth_Attribute_Specification; 676 677 procedure Synth_Subprogram_Declaration 678 (Syn_Inst : Synth_Instance_Acc; Subprg : Node) 679 is 680 Inter : Node; 681 begin 682 if Is_Second_Subprogram_Specification (Subprg) then 683 -- Already handled. 684 return; 685 end if; 686 687 Inter := Get_Interface_Declaration_Chain (Subprg); 688 while Inter /= Null_Node loop 689 Synth_Declaration_Type (Syn_Inst, Inter); 690 Inter := Get_Chain (Inter); 691 end loop; 692 end Synth_Subprogram_Declaration; 693 694 procedure Synth_Convertible_Declarations (Syn_Inst : Synth_Instance_Acc) 695 is 696 use Vhdl.Std_Package; 697 begin 698 Create_Subtype_Object 699 (Syn_Inst, Convertible_Integer_Type_Definition, 700 Get_Subtype_Object (Syn_Inst, Universal_Integer_Type_Definition)); 701 Create_Subtype_Object 702 (Syn_Inst, Convertible_Real_Type_Definition, 703 Get_Subtype_Object (Syn_Inst, Universal_Real_Type_Definition)); 704 end Synth_Convertible_Declarations; 705 706 function Create_Package_Instance (Parent_Inst : Synth_Instance_Acc; 707 Pkg : Node) 708 return Synth_Instance_Acc 709 is 710 Syn_Inst : Synth_Instance_Acc; 711 begin 712 Syn_Inst := Make_Instance (Parent_Inst, Pkg); 713 if Get_Kind (Get_Parent (Pkg)) = Iir_Kind_Design_Unit then 714 -- Global package. 715 Create_Package_Object (Parent_Inst, Pkg, Syn_Inst, True); 716 else 717 -- Local package: check elaboration order. 718 Create_Package_Object (Parent_Inst, Pkg, Syn_Inst, False); 719 end if; 720 return Syn_Inst; 721 end Create_Package_Instance; 722 723 procedure Synth_Package_Declaration 724 (Parent_Inst : Synth_Instance_Acc; Pkg : Node) 725 is 726 Syn_Inst : Synth_Instance_Acc; 727 begin 728 if Is_Uninstantiated_Package (Pkg) then 729 -- Nothing to do (yet) for uninstantiated packages. 730 return; 731 end if; 732 733 Syn_Inst := Create_Package_Instance (Parent_Inst, Pkg); 734 735 Synth_Declarations (Syn_Inst, Get_Declaration_Chain (Pkg)); 736 if Pkg = Vhdl.Std_Package.Standard_Package then 737 Synth_Convertible_Declarations (Syn_Inst); 738 end if; 739 end Synth_Package_Declaration; 740 741 procedure Synth_Package_Body 742 (Parent_Inst : Synth_Instance_Acc; Pkg : Node; Bod : Node) 743 is 744 Pkg_Inst : Synth_Instance_Acc; 745 begin 746 if Is_Uninstantiated_Package (Pkg) then 747 -- Nothing to do (yet) for uninstantiated packages. 748 return; 749 end if; 750 751 Pkg_Inst := Get_Package_Object (Parent_Inst, Pkg); 752 753 Synth_Declarations (Pkg_Inst, Get_Declaration_Chain (Bod)); 754 end Synth_Package_Body; 755 756 procedure Synth_Generics_Association (Sub_Inst : Synth_Instance_Acc; 757 Syn_Inst : Synth_Instance_Acc; 758 Inter_Chain : Node; 759 Assoc_Chain : Node) 760 is 761 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 762 Inter : Node; 763 Inter_Type : Type_Acc; 764 Assoc : Node; 765 Assoc_Inter : Node; 766 Actual : Node; 767 Val : Valtyp; 768 begin 769 Assoc := Assoc_Chain; 770 Assoc_Inter := Inter_Chain; 771 while Is_Valid (Assoc) loop 772 Inter := Get_Association_Interface (Assoc, Assoc_Inter); 773 case Iir_Kinds_Interface_Declaration (Get_Kind (Inter)) is 774 when Iir_Kind_Interface_Constant_Declaration => 775 Synth_Declaration_Type (Sub_Inst, Inter); 776 Inter_Type := Get_Subtype_Object (Sub_Inst, Get_Type (Inter)); 777 778 case Get_Kind (Assoc) is 779 when Iir_Kind_Association_Element_Open => 780 Actual := Get_Default_Value (Inter); 781 Val := Synth_Expression_With_Type 782 (Sub_Inst, Actual, Inter_Type); 783 when Iir_Kind_Association_Element_By_Expression => 784 Actual := Get_Actual (Assoc); 785 Val := Synth_Expression_With_Type 786 (Syn_Inst, Actual, Inter_Type); 787 when others => 788 raise Internal_Error; 789 end case; 790 791 Val := Synth_Subtype_Conversion 792 (Ctxt, Val, Inter_Type, True, Assoc); 793 794 pragma Assert (Is_Static (Val.Val)); 795 796 Create_Object (Sub_Inst, Inter, Val); 797 798 when Iir_Kind_Interface_Package_Declaration => 799 declare 800 Actual : constant Iir := 801 Strip_Denoting_Name (Get_Actual (Assoc)); 802 Pkg_Inst : Synth_Instance_Acc; 803 begin 804 Pkg_Inst := Get_Package_Object (Sub_Inst, Actual); 805 Create_Package_Interface (Sub_Inst, Inter, Pkg_Inst); 806 end; 807 808 when Iir_Kind_Interface_Variable_Declaration 809 | Iir_Kind_Interface_File_Declaration 810 | Iir_Kind_Interface_Signal_Declaration 811 | Iir_Kind_Interface_Quantity_Declaration 812 | Iir_Kind_Interface_Terminal_Declaration => 813 raise Internal_Error; 814 815 when Iir_Kinds_Interface_Subprogram_Declaration 816 | Iir_Kind_Interface_Type_Declaration => 817 raise Internal_Error; 818 end case; 819 820 Next_Association_Interface (Assoc, Assoc_Inter); 821 end loop; 822 end Synth_Generics_Association; 823 824 procedure Synth_Package_Instantiation 825 (Parent_Inst : Synth_Instance_Acc; Pkg : Node) 826 is 827 Bod : constant Node := Get_Instance_Package_Body (Pkg); 828 Sub_Inst : Synth_Instance_Acc; 829 begin 830 Sub_Inst := Create_Package_Instance (Parent_Inst, Pkg); 831 832 Synth_Generics_Association 833 (Sub_Inst, Parent_Inst, 834 Get_Generic_Chain (Pkg), Get_Generic_Map_Aspect_Chain (Pkg)); 835 836 Synth_Declarations (Sub_Inst, Get_Declaration_Chain (Pkg)); 837 838 if Bod /= Null_Node then 839 -- Macro expanded package instantiation. 840 raise Internal_Error; 841 else 842 -- Shared body 843 declare 844 Uninst : constant Node := Get_Uninstantiated_Package_Decl (Pkg); 845 Uninst_Bod : constant Node := Get_Package_Body (Uninst); 846 begin 847 Set_Uninstantiated_Scope (Sub_Inst, Uninst); 848 -- Synth declarations of (optional) body. 849 if Uninst_Bod /= Null_Node then 850 Synth_Declarations 851 (Sub_Inst, Get_Declaration_Chain (Uninst_Bod)); 852 end if; 853 end; 854 end if; 855 end Synth_Package_Instantiation; 856 857 procedure Synth_Variable_Declaration (Syn_Inst : Synth_Instance_Acc; 858 Decl : Node; 859 Is_Subprg : Boolean) 860 is 861 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 862 Def : constant Node := Get_Default_Value (Decl); 863 Decl_Type : constant Node := Get_Type (Decl); 864 Init : Valtyp; 865 Obj_Typ : Type_Acc; 866 Wid : Wire_Id; 867 begin 868 Synth_Declaration_Type (Syn_Inst, Decl); 869 if Get_Kind (Decl_Type) = Iir_Kind_Protected_Type_Declaration then 870 Error_Msg_Synth 871 (+Decl, "protected type variable is not synthesizable"); 872 Set_Error (Syn_Inst); 873 Create_Object (Syn_Inst, Decl, No_Valtyp); 874 return; 875 end if; 876 877 Obj_Typ := Get_Subtype_Object (Syn_Inst, Decl_Type); 878 if not Obj_Typ.Is_Synth 879 and then not Get_Instance_Const (Syn_Inst) 880 then 881 Error_Msg_Synth 882 (+Decl, "variable with access type is not synthesizable"); 883 -- FIXME: use a poison value ? 884 Create_Object (Syn_Inst, Decl, Create_Value_Default (Obj_Typ)); 885 else 886 if Is_Valid (Def) then 887 Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ); 888 Init := Synth_Subtype_Conversion 889 (Ctxt, Init, Obj_Typ, False, Decl); 890 if not Is_Subprg 891 and then not Is_Static (Init.Val) 892 then 893 Error_Msg_Synth 894 (+Decl, "signals cannot be used in default value of " 895 & "this variable"); 896 end if; 897 else 898 Init := Create_Value_Default (Obj_Typ); 899 end if; 900 if Get_Instance_Const (Syn_Inst) then 901 Init := Strip_Alias_Const (Init); 902 Init := Unshare (Init, Current_Pool); 903 Create_Object (Syn_Inst, Decl, Init); 904 else 905 Create_Wire_Object (Syn_Inst, Wire_Variable, Decl); 906 Create_Var_Wire (Syn_Inst, Decl, Init); 907 Wid := Get_Value (Syn_Inst, Decl).Val.W; 908 if Is_Subprg then 909 if Is_Static (Init.Val) then 910 Phi_Assign_Static (Wid, Get_Memtyp (Init)); 911 else 912 Phi_Assign_Net (Ctxt, Wid, Get_Net (Ctxt, Init), 0); 913 end if; 914 end if; 915 end if; 916 end if; 917 end Synth_Variable_Declaration; 918 919 procedure Synth_Signal_Declaration (Syn_Inst : Synth_Instance_Acc; 920 Decl : Node) 921 is 922 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 923 Def : constant Iir := Get_Default_Value (Decl); 924 -- Slot : constant Object_Slot_Type := Get_Info (Decl).Slot; 925 Init : Valtyp; 926 Obj_Typ : Type_Acc; 927 begin 928 Synth_Declaration_Type (Syn_Inst, Decl); 929 if Get_Kind (Get_Parent (Decl)) = Iir_Kind_Package_Declaration then 930 Error_Msg_Synth (+Decl, "signals in packages are not supported"); 931 -- Avoid elaboration error. 932 Create_Object (Syn_Inst, Decl, No_Valtyp); 933 return; 934 end if; 935 936 Create_Wire_Object (Syn_Inst, Wire_Signal, Decl); 937 if Is_Valid (Def) then 938 Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); 939 Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Typ); 940 Init := Synth_Subtype_Conversion (Ctxt, Init, Obj_Typ, False, Decl); 941 if not Is_Static (Init.Val) then 942 Error_Msg_Synth (+Decl, "signals cannot be used in default value " 943 & "of a signal"); 944 end if; 945 else 946 Init := No_Valtyp; 947 end if; 948 Create_Var_Wire (Syn_Inst, Decl, Init); 949 end Synth_Signal_Declaration; 950 951 procedure Synth_Object_Alias_Declaration 952 (Syn_Inst : Synth_Instance_Acc; Decl : Node) 953 is 954 Ctxt : constant Context_Acc := Get_Build (Syn_Inst); 955 Atype : constant Node := Get_Declaration_Type (Decl); 956 Off : Value_Offsets; 957 Dyn : Stmts.Dyn_Name; 958 Res : Valtyp; 959 Obj_Typ : Type_Acc; 960 Base : Valtyp; 961 Typ : Type_Acc; 962 begin 963 -- Subtype indication may not be present. 964 if Atype /= Null_Node then 965 Synth_Subtype_Indication (Syn_Inst, Atype); 966 Obj_Typ := Get_Subtype_Object (Syn_Inst, Atype); 967 else 968 Obj_Typ := null; 969 end if; 970 971 Stmts.Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), 972 Base, Typ, Off, Dyn); 973 pragma Assert (Dyn.Voff = No_Net); 974 if Base.Val.Kind = Value_Net then 975 -- Object is a net if it is not writable. Extract the 976 -- bits for the alias. 977 Res := Create_Value_Net 978 (Build2_Extract (Ctxt, Base.Val.N, Off.Net_Off, Typ.W), 979 Typ); 980 else 981 Res := Create_Value_Alias (Base, Off, Typ); 982 end if; 983 if Obj_Typ /= null then 984 Res := Synth_Subtype_Conversion (Ctxt, Res, Obj_Typ, True, Decl); 985 end if; 986 Create_Object (Syn_Inst, Decl, Res); 987 end Synth_Object_Alias_Declaration; 988 989 procedure Synth_Declaration (Syn_Inst : Synth_Instance_Acc; 990 Decl : Node; 991 Is_Subprg : Boolean; 992 Last_Type : in out Node) is 993 begin 994 case Get_Kind (Decl) is 995 when Iir_Kind_Variable_Declaration => 996 Synth_Variable_Declaration (Syn_Inst, Decl, Is_Subprg); 997 when Iir_Kind_Interface_Variable_Declaration => 998 -- Ignore default value. 999 Create_Wire_Object (Syn_Inst, Wire_Variable, Decl); 1000 Create_Var_Wire (Syn_Inst, Decl, No_Valtyp); 1001 when Iir_Kind_Constant_Declaration => 1002 Synth_Constant_Declaration (Syn_Inst, Decl, Is_Subprg, Last_Type); 1003 when Iir_Kind_Signal_Declaration => 1004 pragma Assert (not Is_Subprg); 1005 Synth_Signal_Declaration (Syn_Inst, Decl); 1006 when Iir_Kind_Object_Alias_Declaration => 1007 Synth_Object_Alias_Declaration (Syn_Inst, Decl); 1008 when Iir_Kind_Anonymous_Signal_Declaration => 1009 -- Anonymous signals created by inertial associations are 1010 -- simply ignored. 1011 null; 1012 when Iir_Kind_Procedure_Declaration 1013 | Iir_Kind_Function_Declaration => 1014 Synth_Subprogram_Declaration (Syn_Inst, Decl); 1015 when Iir_Kind_Procedure_Body 1016 | Iir_Kind_Function_Body => 1017 null; 1018 when Iir_Kind_Non_Object_Alias_Declaration => 1019 null; 1020 when Iir_Kind_Attribute_Declaration => 1021 -- Nothing to do: the type is a type_mark, not a subtype 1022 -- indication. 1023 null; 1024 when Iir_Kind_Attribute_Specification => 1025 Synth_Attribute_Specification (Syn_Inst, Decl); 1026 when Iir_Kind_Type_Declaration => 1027 Synth_Type_Definition (Syn_Inst, Get_Type_Definition (Decl)); 1028 when Iir_Kind_Anonymous_Type_Declaration => 1029 Synth_Anonymous_Type_Definition 1030 (Syn_Inst, Get_Type_Definition (Decl), 1031 Get_Subtype_Definition (Decl)); 1032 when Iir_Kind_Subtype_Declaration => 1033 Synth_Declaration_Type (Syn_Inst, Decl); 1034 when Iir_Kind_Component_Declaration => 1035 null; 1036 when Iir_Kind_File_Declaration => 1037 declare 1038 F : File_Index; 1039 Res : Valtyp; 1040 Obj_Typ : Type_Acc; 1041 begin 1042 F := Synth.Files_Operations.Elaborate_File_Declaration 1043 (Syn_Inst, Decl); 1044 Obj_Typ := Get_Subtype_Object (Syn_Inst, Get_Type (Decl)); 1045 Res := Create_Value_File (Obj_Typ, F); 1046 Create_Object (Syn_Inst, Decl, Res); 1047 end; 1048 when Iir_Kind_Protected_Type_Body => 1049 null; 1050 when Iir_Kind_Psl_Default_Clock => 1051 -- Ignored; directly used by PSL directives. 1052 null; 1053 when Iir_Kind_Use_Clause => 1054 null; 1055 when Iir_Kind_Configuration_Specification => 1056 null; 1057 when Iir_Kind_Signal_Attribute_Declaration => 1058 -- Not supported by synthesis. 1059 null; 1060 when others => 1061 Vhdl.Errors.Error_Kind ("synth_declaration", Decl); 1062 end case; 1063 end Synth_Declaration; 1064 1065 procedure Synth_Declarations (Syn_Inst : Synth_Instance_Acc; 1066 Decls : Iir; 1067 Is_Subprg : Boolean := False) 1068 is 1069 Decl : Node; 1070 Last_Type : Node; 1071 begin 1072 Last_Type := Null_Node; 1073 Decl := Decls; 1074 while Is_Valid (Decl) loop 1075 Synth_Declaration (Syn_Inst, Decl, Is_Subprg, Last_Type); 1076 1077 exit when Is_Error (Syn_Inst); 1078 1079 Decl := Get_Chain (Decl); 1080 end loop; 1081 end Synth_Declarations; 1082 1083 procedure Finalize_Signal (Syn_Inst : Synth_Instance_Acc; Decl : Node) 1084 is 1085 use Netlists.Gates; 1086 Vt : Valtyp; 1087 Gate_Net : Net; 1088 Gate : Instance; 1089 Drv : Net; 1090 Def_Val : Net; 1091 begin 1092 Vt := Get_Value (Syn_Inst, Decl); 1093 if Vt = No_Valtyp then 1094 pragma Assert (Is_Error (Syn_Inst)); 1095 return; 1096 end if; 1097 if Vt.Val.Kind = Value_Net then 1098 -- Could be a net for in ports. 1099 return; 1100 end if; 1101 1102 Finalize_Assignment (Get_Build (Syn_Inst), Vt.Val.W); 1103 1104 Gate_Net := Get_Wire_Gate (Vt.Val.W); 1105 Gate := Get_Net_Parent (Gate_Net); 1106 case Get_Id (Gate) is 1107 when Id_Signal 1108 | Id_Output 1109 | Id_Inout => 1110 Drv := Get_Input_Net (Gate, 0); 1111 Def_Val := No_Net; 1112 when Id_Isignal 1113 | Id_Ioutput 1114 | Id_Iinout => 1115 Drv := Get_Input_Net (Gate, 0); 1116 Def_Val := Get_Input_Net (Gate, 1); 1117 when others => 1118 -- Todo: output ? 1119 raise Internal_Error; 1120 end case; 1121 if Drv = No_Net then 1122 if Is_Connected (Get_Output (Gate, 0)) then 1123 -- No warning if the signal is not used. 1124 -- TODO: maybe simply remove it. 1125 if Def_Val = No_Net then 1126 Warning_Msg_Synth 1127 (+Decl, "%n is never assigned and has no default value", 1128 (1 => +Decl)); 1129 else 1130 Warning_Msg_Synth (+Decl, "%n is never assigned", (1 => +Decl)); 1131 end if; 1132 end if; 1133 if Def_Val = No_Net then 1134 Def_Val := Build_Const_X (Get_Build (Syn_Inst), 1135 Get_Width (Gate_Net)); 1136 end if; 1137 Connect (Get_Input (Gate, 0), Def_Val); 1138 end if; 1139 1140 Free_Wire (Vt.Val.W); 1141 end Finalize_Signal; 1142 1143 procedure Finalize_Declaration 1144 (Syn_Inst : Synth_Instance_Acc; Decl : Node; Is_Subprg : Boolean) is 1145 begin 1146 case Get_Kind (Decl) is 1147 when Iir_Kind_Variable_Declaration 1148 | Iir_Kind_Interface_Variable_Declaration => 1149 if not Get_Instance_Const (Syn_Inst) then 1150 declare 1151 Vt : constant Valtyp := Get_Value (Syn_Inst, Decl); 1152 begin 1153 if Vt /= No_Valtyp 1154 and then Vt.Val.Kind = Value_Wire 1155 then 1156 Finalize_Assignment (Get_Build (Syn_Inst), Vt.Val.W); 1157 Free_Wire (Vt.Val.W); 1158 end if; 1159 end; 1160 end if; 1161 when Iir_Kind_Constant_Declaration => 1162 null; 1163 when Iir_Kind_Signal_Declaration 1164 | Iir_Kind_Interface_Signal_Declaration => 1165 pragma Assert (not Is_Subprg); 1166 Finalize_Signal (Syn_Inst, Decl); 1167 when Iir_Kind_Anonymous_Signal_Declaration => 1168 null; 1169 when Iir_Kind_Object_Alias_Declaration => 1170 null; 1171 when Iir_Kind_Procedure_Declaration 1172 | Iir_Kind_Function_Declaration => 1173 null; 1174 when Iir_Kind_Procedure_Body 1175 | Iir_Kind_Function_Body => 1176 null; 1177 when Iir_Kind_Non_Object_Alias_Declaration => 1178 null; 1179 when Iir_Kind_Attribute_Declaration => 1180 null; 1181 when Iir_Kind_Attribute_Specification => 1182 null; 1183 when Iir_Kind_Type_Declaration => 1184 null; 1185 when Iir_Kind_Anonymous_Type_Declaration => 1186 null; 1187 when Iir_Kind_Subtype_Declaration => 1188 null; 1189 when Iir_Kind_Component_Declaration => 1190 null; 1191 when Iir_Kind_File_Declaration => 1192 null; 1193 when Iir_Kind_Configuration_Specification => 1194 null; 1195 when Iir_Kind_Psl_Default_Clock => 1196 -- Ignored; directly used by PSL directives. 1197 null; 1198 when Iir_Kind_Signal_Attribute_Declaration => 1199 -- Not supported by synthesis. 1200 null; 1201 when others => 1202 Vhdl.Errors.Error_Kind ("finalize_declaration", Decl); 1203 end case; 1204 end Finalize_Declaration; 1205 1206 procedure Finalize_Declarations (Syn_Inst : Synth_Instance_Acc; 1207 Decls : Iir; 1208 Is_Subprg : Boolean := False) 1209 is 1210 Decl : Iir; 1211 begin 1212 Decl := Decls; 1213 while Is_Valid (Decl) loop 1214 Finalize_Declaration (Syn_Inst, Decl, Is_Subprg); 1215 1216 Decl := Get_Chain (Decl); 1217 end loop; 1218 end Finalize_Declarations; 1219end Synth.Decls; 1220